• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 30 subscribers
  • Views 583 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

tlv320AIC3204 HP output

Madis
Prodigy 100 points
Other Parts Discussed in Thread: TLV320AIC3204

Hello!

I have designed the audio board with tlv320AIC3204 codec.

IOVDD: 3V3, LDOSelect is high. AVDD and DVDD both have 10uF to GND.

I2C control seems to be working. I have verified it by read after write and also with protocol analyser directly from the bus.

For audio interface I have tested I2S and DSP mode, no difference.

Master clock is 12M and sample rate 48K, tested also with 49M/192K

The chip behaves very strange. Output of the HPL and HPR both drive close to the upper power rail (3v3) even without the input data. And another obersvation is, that after connecting DAC outputs to HP amplifiers, AVDD drives up to 2.1V(maybe related somehow...). So I can not really insert any data as the output is stuck to the rail already... I insert the script Im using, maybe somebody can help me out, I have been rearranging the code in many different ways without any success...:

-------------------------------------------------------------------------------------------------------------

//perform the hardware reset, this code drives the codecs HW reset line on/off
FPGA_WD(FPGAreg(CODEC_CONTROL_REGISTER), 1);
vTaskDelay(pdMS_TO_TICKS(100));
FPGA_WD(FPGAreg(CODEC_CONTROL_REGISTER), 0);
vTaskDelay(pdMS_TO_TICKS(100));

//perform the software reset
CodecWrite(ucChannel, 0x00, 0x00); //select page 0
CodecWrite(ucChannel, 0x01, 0x01); //software reset
vTaskDelay(pdMS_TO_TICKS(10));

-------------------------------------------------------------------------------------------------------------

CodecWrite(ucChannel, 0, 0); //select page 0

CodecWrite(ucChannel, 0x0B, 0x81); //Power up the NDAC divider with value 1
CodecWrite(ucChannel, 0x0C, 0x82); //Power up the MDAC divider with value 2
CodecWrite(ucChannel, 0x0D, 0x00); //Program the OSR of DAC to 128
CodecWrite(ucChannel, 0x0E, 0x80);

CodecWrite(ucChannel, 0x12, 0x01); //Power up the NADC divider with value 1
CodecWrite(ucChannel, 0x13, 0x02); //Power up the MADC divider with value 2
CodecWrite(ucChannel, 0x14, 0x80); //ADC oversampling

-------------------------------------------------------------------------------------------------------------

CodecWrite(ucChannel, 0x1B, 0x40); //16 bit audio, DSP mode interface
CodecWrite(ucChannel, 0x1C, 0x01); //data offset: 1
CodecWrite(ucChannel, 0x1D, 0x00); //no clock invert

-------------------------------------------------------------------------------------------------------------

CodecWrite(ucChannel, 0x00, 0x01); //select page 1
CodecWrite(ucChannel, 0x02, 0x09); //Power up AVDD LDO
CodecWrite(ucChannel, 0x01, 0x08); //Disable Internal Crude AVdd in presence of external AVdd supply
vTaskDelay(pdMS_TO_TICKS(10));
CodecWrite(ucChannel, 0x02, 0x01); //Enable Master Analog Power Control

CodecWrite(ucChannel, 0x47, 0x32); //Set the input power-up time to 3.1ms (for ADC) (6.3?)
CodecWrite(ucChannel, 0x7B, 0x01); //Set the REF charging time to 40ms
CodecWrite(ucChannel, 0x0A, 0x3B); //Set the Input Common Mode to 0.9V //0x3B

-------------------------------------------------------------------------------------------------------------

CodecWrite(ucChannel, 0x00, 0x00); //select page 0


CodecWrite(ucChannel, 0x44, 0x00); //disable the DRC
CodecWrite(ucChannel, 0x3C, 0x01); //Set the DAC Mode to PRB_P7

CodecWrite(ucChannel, 0x00, 0x01); //select page 1

CodecWrite(ucChannel, 0x03, 0x08); //Set the DAC PTM mode to PTM_P3/4 //8 PTM1, 4 PTM2
CodecWrite(ucChannel, 0x04, 0x08);
CodecWrite(ucChannel, 0x14, 0x25); //HP soft stepping settings for optimal pop performance at power up

CodecWrite(ucChannel, 0x09, 0x30); //Power up HPL and HPR drivers/ LOL LOR

CodecWrite(ucChannel, 0x10, 0x00); //Set the HPL gain to 0dB/unmute //0x1D
CodecWrite(ucChannel, 0x11, 0x00); //Set the HPR gain to 0dB/unmute

//here the HP outputs are ~CM voltage ~1.6V


CodecWrite(ucChannel, 0x00, 0x00); //select page 0

CodecWrite(ucChannel, 0x41, 0x00); //left dac gain = 0dB //0x30 max
CodecWrite(ucChannel, 0x42, 0x00); //right dac gain = 0dB
CodecWrite(ucChannel, 0x3F, 0xD4); //Power up the Left and Right DAC Channels //D6
CodecWrite(ucChannel, 0x40, 0x00); //unmute

//still no problem, but after connecting DAC outputs to the HP drivers, HP output jumps to the upper rail


CodecWrite(ucChannel, 0x00, 0x01); //select page 1

CodecWrite(ucChannel, 0x0C, 0x08); //Route Left DAC to HPL

//after connecting Right DAC to HPR AVDD jumps to 2.04V
CodecWrite(ucChannel, 0x0D, 0x08); //Route Right DAC to HPR //0x08

//wait for 2.5sec for soft stepping to take effect or poll reg 63 b6..7
vTaskDelay(pdMS_TO_TICKS(2500));
//CodecRead(ucChannel, 0x3F, &data);

CodecWrite(ucChannel, 0x16, 0x75); //IN1L to HPL Volume Control Register
CodecWrite(ucChannel, 0x17, 0x75); //IN1R to HPR Volume Control Register mute

CodecWrite(ucChannel, 0x18, 0x28); //Mixer Amplifier Left Volume Control Register
CodecWrite(ucChannel, 0x19, 0x28); //Mixer Amplifier Right Volume Control Register mute

-------------------------------------------------------------------------------------------------------------

Thank you,

Madis

  • 0
    TI__Guru* 84915 points

    Hi, Madis,

    I already checked your entire register configuration in the TLV320AIC3204EVM. I have some observations about your register settings.

    CodecWrite(ucChannel, 0x1B, 0x00); //16 bit audio, I2S mode interface
    CodecWrite(ucChannel, 0x1C, 0x00); //data offset: 0

    I changed registers 0x1B and 0x1C to make the test. You must be sure that your data has 1 BCLK offset to obtain a correct behavior of the codec.

    CodecWrite(ucChannel, 0x0A, 0x0B); //Set the Input Common Mode to 0.9V //0x3B

    I used a common mode voltage of 0.9V and the HP outputs level descended.

    CodecWrite(ucChannel, 0x10, 0x00); //Set the HPL gain to 0dB/unmute //0x1D
    CodecWrite(ucChannel, 0x11, 0x00); //Set the HPR gain to 0dB/unmute

    Finally, I tested the HP output with different volume values and it worked correctly in all the cases.

    Could you check this changes please?

    Please let me know if the problem persists.

    Best regards,

    Luis Fernando Rodríguez S.

  • 0 in reply to Luis Fernando Rodriguez S.
    Prodigy 100 points
    Hi!

    Thank you for the reply!

    As you verified the code we addressed the hw issues once more. We are using codec reference output for another chip reference input. And those two did not play nice together. Reference voltage got rised to ~1.65V. I overlooked it before as I thought it is HP/Line reference, which got set to 1.65. But this reference should be really 0.9 (or 0.75) according to the datasheet.

    After fixing the reference (additional buffer), everything is fine. As the result we have full set of audio interfaces and different sample rates available in FPGA as we had to test those all. And codec evaluation kit arriving probably tomorrow, can give it to employer of the month or something:-)

    Thanks,
    Madis