TLV320ADC3001 AOSR limits

Hi, Mike,

The AOSR limits  from the datasheet are specified to ensure the correct behavior of the ADC, So I recommend to try following the condition. 

Best Regards,

  -Diego Meléndez López
   Audio Applications Engineer

Is it possible to use a built-in decimation filter with a sample rate of 16 kHz? The decimation filter is one of the most compelling reasons for using this ADC. The description on the first page of the datasheet states that the ADC supports sampling rates from 8 kHz to 96 kHz. In section 10.3.8, it again states that sampling rates from 8 kHz are supported, and then in the third paragraph of section 10.8.3 the decimation filter is described as follows:

The integrated digital decimation filter removes high-frequency content and downsamples the audio data from an initial sampling rate of 128 fS to the final output sampling rate of fS. The decimation filter provides a linear phase output response with a group delay of 17/fS. The –3-dB bandwidth of the decimation filter extends to 0.45 fS and scales with the sample rate (fS). The filter has minimum 73-dB attenuation over the stop band from 0.55 fS to 64 fS. Independent digital highpass filters are also included with each ADC channel, with a corner frequency that can be set independently by programmable coefficients or can be disabled entirely.

Because of the oversampling nature of the audio ADC and the integrated digital decimation filtering, requirements for analog anti-aliasing filtering are relaxed. The TLV320ADC3001 integrates a second-order analog anti-aliasing filter with 20-dB attenuation at 1 MHz. This filter, combined with the digital decimation filter, provides sufficient anti-aliasing filtering without requiring additional external components.

There is no answer yet to my question in the previous post.

On the TLV320ADC3001, is it possible to use a built-in decimation filter with a sample rate of 16 kHz? 

Hello, Bob,

The TLV320ADC3001 is able to generate a sample rate from 8KHz to 96KHz. It would be necessary to configure the PLL and clock dividers correctly as the 10.3.7 Audio Clock Generation section of datasheet explains.

Best regards,
Luis Fernando Rodríguez S.

Hi Luis,

Thank you for the reply.  I understand how to set the registers to produce a 16 kHz sample rate.  My question is regarding the use of a built-in decimation filter with a sample rate of 16 kHz.  Is it possible to use a built-in decimation filter with a sample rate of 16 kHz?

Thanks,

-Bob Heise

Hi, Bob,

The internal decimation filter downsamples the audio data from an initial sampling rate of 128 fs to the final output sampling rate of fs. So, this filter only adjusts the initial frequency to the sampling rate. Section 8.5 Electrical Characteristics explains how this filter works when the sampling rate is configured at fs = 48KHz. However, this filter doesn't need an individual sample rate to work.

Please let me know if you have more questions or comments.

Best regards,
Luis Fernando Rodríguez S.

Hi Luis,

My question has still not been answered.  I'm looking for a "yes" or "no" answer.  Is it possible to use a built-in decimation filter with a sample rate of 16 kHz?

Regards,

-Bob Heise

Thank you Luis.
I would very much like to use decimation filter A with a 16 KHz sample rate.
Can you please address the condition on page 75 of the datasheet regarding the use of the built-in decimation filters?

In all cases, AOSR is limited in its range by the following condition:
2.8 MHz < AOSR × ADC_fS < 6.2 MHz

With AOSR = 128, AOSR × ADC_fS = 128 × 16 kHz = 2.048 MHz which is outside the required range.

Hi, Bob,

I have been searching for more information about this range.

It seems that this is a mistake in the datasheet. The first limit (2.8MHz) is much lower. The low number in the equation of page 75 should be 1MHz. So, there won't be problem if you use AOSR = 128. I will notify this to correct it.

Thank you for the observation.

Best regards,
Luis Fernando Rodríguez S.

Thank you very much Luis.
That is the information I was looking for!

Hello Luis, thanks for answering the question, I'd recently collided with this AOSR limits issue and had been thinking a lot, until I found this answer of yours. In particular, I'd like to use a 12.8 kHz sampling frequency with the Decimation Filter A and an AOSR of 128. However I've noticed, that the mistake in the datasheet is still not corrected - Rev. D is still the most recent version of the document and it still says that 2.8 MHz is the lowest limit for AOSR x Fs. Confusing, eh? :)

Thanks again for your help.

Kind regards,

Artyom Ivanov

Hi, Artyom,

Welcome to E2E and thank you for your interest in our products!

This use to be a confusion on the datasheet. Actually, the mentioned range ( 2.8 MHz < AOSR × ADC_fS < 6.2 MHz ) only applies when the sampling frequency is 44.1KHz or 48KHz. Basically, this range is determined by the AOSR value which is not recommended to be less than 64 or more than 128. So, if you are using a sampling frequency of 12.8KHz and an AOSR of 128, there shouldn't be any issue.

Please let me know if you require more information and if you have more questions.

Best regards,
Luis Fernando Rodríguez S.