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Using 512X MCLK with MC57xxPSIA

Howard Chamberlin
Prodigy 130 points
Other Parts Discussed in Thread: TAS5727EVM, TAS5727, DIR9001, PCM1808

I am using a MC57xxPSIA with a TAS5727EVM attached.  I want to use the ADC on-board the MC57xxPSIA, a 512X MCLK (24.576MHz), and a sample rate (LRCLK) of 48KHz.  

As received the board produces a 256X MCLK and 48KHz sample rate.  Installing JP1 (which is supposed to select a 512X MCLK frequency) seems to have no effect on the MCLK frequency - it remains at 12.288MHz.

So is it possible to use internal clocking from the on-board crystal, the on-board ADC, and run at 512X MCLK?  Eventually the MC57xxPSIA will need to talk to a TAS5727 on my application board which also uses MCLK for other functions.

HAL

  • 0
    TI__Guru 57800 points

    Hi, Howard,

    The MCLK of the MC57xxPSIA board is generated effectively in DIR9001. This device takes the SPDIF signal and converts it to I²S format. when using analog inputs, the data is converted with the PCM1808, but the MCLK, SCLK and LRCK comes from the DIR9001.

    The usage of JP1 is effective only when the DIR9001 is configured to use the PLL source clock (pin 28 low). In MC57xxPSIA board, the circuit of the DIR9001 is configured in Automatic clock selection mode. This mode enables selection of the clock source automatically, using the DIR9001 ERROR status. The PLL source clock is output when ERROR = L; the XTI source is output when ERROR = H.

    ERROR signal will be High if no SPDIF signal is present at the input of the device. So, in order to use 512xFs MCLK, you need to have an SPDIF signal as input. Another option will be to change Y2 to a 24.576 xtal, or remove R32 and place a resistor to GND connected directly to pin 28.

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • 0 in reply to Diego Melendez
    Prodigy 130 points

    Thank you for researching this issue and answering.

    I have already tried changing the crystal.  An undesirable side-effect though is that the sample rate of the system then changes to 96KHz. Thus LRCLK becomes 96KHz and BCLK becomes 6.144MHz.  

    The issue with forcing CKSEL low is that the frequency of MCLK and those derived from it becomes uncertain - referring to section 8.3.4, line 4 in the DIR9001 datasheet.  Its a pity that the VCO doesn't instead lock to the crystal oscillatlor when there is no SPDIF signal..

    I think that to get moving, I need to figure out a way to provide my test signals via SPDIF rather than analog.

    Howard Chamberlin