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TPA5050 Complete Update Register

na na78
Guru 16770 points

Hi

If we write 1 to complete Update register, how to back to 0?

After required delay accomplished, this register becomes 0 automatically?

BestRegards

  • 0
    TI__Guru* 84915 points
    Hi, na,

    You should write a '0' in LSB (D0). There's no mention of a automatic change of this bit after required delay is accomplished.

    Best regards,
    Luis Fernando Rodríguez S.
  • 0 in reply to Luis Fernando Rodriguez S.
    Guru 16770 points
    Hi Luis

    Thank you for your reply.
    We understood we should write a '0' in LSB of Complete Update Register.

    Can we ask some new questions about that?

    1.
    Mute starts at the timing of writing '1' in LSB(D0) of Complete Update Register, OK?
    In other words, is the trigger of mute writing '1' in complete update register?

    2.
    After writing '1' in LSB(D0) of Complete Update Register, '1' in LSB would remain in the register.

    Using multiple byte write, complete update register would be updated by 0x01 at the end.

    When should we write '0' in complete update register?
    Can we write '0' in the register immediately after writing '1'?
    Or should we wait until the mute ends?

    We are afraid if writing '0' in the complete update register leads to unexpected operation or not.

    3.
    Is it correct way that we use single byte write when we reset the complete update register with '0'?

    Best Regards
  • 0 in reply to na na78
    TI__Guru* 84915 points

    Hi, na,

    1. Effectively, once '1' is written in bit D0 of register 0x08, the mute is applied as described in Complete Update Register (0x08) section of datasheet.

    2. Please ensure that the mute is end to write '0' in this register. If '0' is written before mute ends, the operation could be interrupted.

    3. Yes, there's no problem. This register can be written individually with single byte write.

    Best regards,
    Luis Fernando Rodríguez S.

  • 0 in reply to Luis Fernando Rodriguez S.
    Guru 16770 points

    Hi Luis

    Thank you for your help.

    Sorry for questioning many of times.

    We summarized the steps for setting up the delay as a following flow chart, for our understanding.

    Could you please give us a feedback if the flow chart has problem or not?
    Is this flow chart recommended?

    Best Regards

  • 0 in reply to na na78
    TI__Guru* 84915 points
    Hi, na,

    That's correct. Phase 1 is used for multiple register writing. This configuration would be made for a complete configuration of the device. Then, phase 2 is used for a specific register configuration (in this case, complete update register). Finally, the phase 3 would be used for new settings.

    It is all in order.

    Please let me know if you have more questions or comments.

    Best regards,
    Luis Fernando Rodríguez S.