TLV320AIC33 in Master mode sometimes produces BCLK with Duty cycle ~ 37% / 63 % instead of nominal 50% / 50%.

Sergei Vereskov

Other Parts Discussed in Thread: TLV320AIC33

Hello!

What could be the reason for the fact, that TLV320AIC33 in Master mode sometimes ( approximately 1-2 out of 10 switch-ons of device in which it is onboard ) produces BCLK with Duty cycle ~ 37% / 63 % instead of nominal 50% / 50% ?

This behaviour causes malfunction of downstream devices.

PLL is enabled and D=0000. MCLK = 18,432 MHz, WCLK = 48 kHz, BCLK = 3,072 MHz, R=1, P=3, K=J=16.

I understand, that its difficult to give an exact reason for such a behaviour, but please give me a hint!

over 7 years ago

0 Luis Fernando Rodriguez S. over 7 years ago

TI__Guru* 84915 points

Hi, Sergei,

This could be related with a register sequencing problem or a PLL configuration issue. Please ensure that the following guidelines are respected:

- The ADC and DAC must be powered down when changing the sample rate.
- The PGAs must be muted before the ADC is powered down.
- When selecting an input, unmute the PGAs after routing the input and powering up the ADC.
- After configuring the PLL, please wait for 10ms before writing the rest of register configuration. This will ensure that the PLL is configured correctly.
- Apply a hardware and software reset after the codec is powered on.

Please let me know if the problem persists.

Best regards,
Luis Fernando Rodríguez S.

0 Sergei Vereskov over 7 years ago in reply to Luis Fernando Rodriguez S.

Intellectual 510 points

Thank You very much for Your help!
It seems, that this advice really helped:
- After configuring the PLL, please wait for 10ms before writing the rest of register configuration. This will ensure that the PLL is configured correctly.

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TLV320AIC33 in Master mode sometimes produces BCLK with Duty cycle ~ 37% / 63 % instead of nominal 50% / 50%.