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TLV320AIC33 - DC offset in recorded digital signal, correct single-ended input connection

Other Parts Discussed in Thread: TLV320AIC33

Hello,

I have two questions about codec TLV320AIC33.

1. I have discovered some oddity about codec power supply. In datasheet on page 2 and 17 is mentioned power supply pin "AVDD_ADC" which should be connected by capacitor to ground. But this pin is not listed in pinout table and physicaly is not placed on any package. Is this pin internaly connected and named as AVDD? Or Is there any other explanation?

2. I am not sure about analog input connection in single ended configuration. I couldn't find any example how to correctly connect input to codec, especialy what to do with unused pin of differential pair (minus pole of input). Now I use RC in serial configuration (0.47uF, 2K2) connected to ground. Everything seemed to be ok (good SNR, THD...), but i have figured out some DC offset (around 10% of input range, PGA 0dB) which is recorded in digital output signal. PGA also affects this offset. Another mystery, there is not the same offset voltage level on both channels however connection (used passives) on stereo input is identical.

Has someone experience with this? I guess that there is some problem with voltage reference between input amplifier and ADC.

  • Hi, Marek,

    Welcome to E2E and thank you for your interest in our products!

    1. Effectively, AVDD_ADC is actually AVDD pin. In some codecs, the AVDD power supply is divided in several pins. So, they are often named as AVDD_ADC or AVDD_DAC. So, make sure that there are decoupling capacitors close to power pins (10uF and 0.1uF are the suggested values). These will ensure that the supplies are regulated correctly and there won't be an issue in ADC and DAC conversions.

    2. Regarding your DC offset, I would suggest several things. Ensure that all your unused analog inputs are connected to a 0.47uF cap to GND. All the inputs are biased, so they shouldn't be connected to GND directly. Ensure that all the used inputs have a 0.47uF DC-blocking capacitor. Finally, in cases of microphone connections, you may take a look at these examples:

    Single-ended:

    Differential:

    Best regards,
    Luis Fernando Rodríguez S.

  • Hi Luis,

    thank you for your response and explanation. In the 1st case, it is clear for me now.

    In the case of the offset problem, as you mentioned, I am sure that I use inputs correctly. I know about internal bias to level 1.35V so all inputs are decoupled by cap 0.47uF. I have tried a few variants on unused input, including only 0.47uF cap connected to GND. In this case, I measured worse THD if I increase signal amplitude (still under maximum allowed level). Especialy, there was distortion on lower half wave of signal. Distortion gets better with RC combination in the same conditions. That is the reason why I use RC.

    I hope that I do not have any problem with power supply. I designed it very carefully and robust. I tried to compare offset measurement with another application of this codec and I can say it has the same result. I can also see DC-offset in recorded signal and it seems to be casual. There is not any fixed voltage level of this offset and it is aslo different between stereo pair on the same codec.

    Thanks and best regards,

    Marek G.

  • Hi, Marek,

    Do you have the same results by using different inputs? If the analog inputs are un-routed to the PGA, do you still have offset at the output?

    Best regards,
    Luis Fernando Rodríguez S.
  • Hi Luis,

    yes, there is a offset by using different inputs (I tried L1 in single ended configuration and L3) even if all of analog inputs are powered off (It has lower voltage level, but it still remains).

    However I found solution of this problem. I totaly forgot about digital highpass feature in this codec which helped me to remove DC-offset.

    I am still not sure if this behavior is correct without active highpass, but with HP it brought me satisfying result.

    Thank you for your time and reply,

    Best regards

    Marek G.