TLV320AIC3100 Initialization requierments for BT to SPK output

Yuri Cherniakov

Other Parts Discussed in Thread: TLV320AIC3100, CC2564

Hi!

The current project i work on involves adding a headset ability to my device using the HSP demo.

I am working with the CC2564 (as master) and the TLV320AIC3100 (as its slave). My MCU is the STM32L476.

During the "etHDSET_Audio_Connection_Indication" i initialize the I2C lines so that the cc2564 is the master, also, i initialize the TLV320AIC3100 and verify this init by generating a beep.

The problem starts when i try to hear the input from the cc2564 on the speaker (that has just beeped after init), i hear nothing from the speaker though i see changes and reaction on the DIN line.

I suspect that there is a possibility that my init is not correct,

Is the beep a conformation for a successful init?

Please advise on how to debug this issue.

over 8 years ago

0 Luis Fernando Rodriguez S. over 8 years ago

TI__Guru* 84915 points

Hi, Yuri,

If the TLV320AIC3100 was able to generate a bit, then the initialization and I2C lines are in order. I suspect that this issue is related with a register configuration or a clocking issue. Could you provide your entire register configuration and the BCLK, WCLK, MCLK an sampling rate values? This is to have a better approach to this issue.

Thank you.

Best regards,
Luis Fernando Rodríguez S.

0 Yuri Cherniakov over 8 years ago in reply to Luis Fernando Rodriguez S.

Expert 1740 points

Hello Luis,

thank you for the response,

I attach a text file with all the information regarding the registers configuration

(structure, addresses and values - all were written and defined according to the datasheet).

Also i have sampled the clocks:

MCLK = 8Mhz

WCLK = 8Khz

BCLK = 256Khz

Fullscreen Codec INIT defines and values.txt Download

// PLL configuration

#define DEVICE_SAMPLE_RATE                               8000
#define MSFACTOR                                         (DEVICE_SAMPLE_RATE / 1000)  // Factor for turning cycles into miliseconds
#define CLK_GEN_MUX_VAL                                 0x03 // Set the REG value so that the PL_CLKIN = Master clock and the Codec_CLKIN = PLL_CLK.
#define PLL_P_AND_R_VAL                                 0xD2 // Set the REG value so that the PLL is enabled, P=5, R=2.
#define PLL_J_VAL                                       0x20 // Set the REG value so that J = 32.
#define PLL_D_VAL_MSB                                   0x00 // Set the REG value so that D = 0.
#define PLL_D_VAL_LSB                                   0x00 
#define NDAC_VAL                                        0x84 // 5 // Set the REG value sp that the NDAC is powered up and DAC NDAC divider = 4 
#define MDAC_VAL                                        0x99 // 85 // Set the REG value sp that the MDAC is powered up and DAC MDAC divider = 25 
#define NADC_VAL                                        0x84 // 5 // Set the REG value sp that the NADC is powered up and DAC NADC divider = 4 
#define MADC_VAL                                        0x99 // 85 // Set the REG value sp that the MADC is powered up and DAC MADC divider = 25 
#define AOSR_VAL                                        0x80 // Set the REG value sp that the AOSR = 128.
#define DOSR_MSB_VAL                                    0x00 // Set the REG value sp that the DOSR = 128. 
#define DOSR_LSB_VAL                                    0x80  



// constant values.
#define TWO_POWER_FIFTEEN                                (1<<15)
#define ENABLE_BEEP                                      0x80
#define MAX_VOL_LEVEL                                    63     // beep generation maximum level.
#define RESET_VAL                                        0x01   // The value written to SOFTWARE_RESET_REG_ADDR to enable sofware restart.

// Value for masking during volume settings
#define BeepVolumeMask                                   0x3F
#define GeneralVolumeMask                                0x7F

// Init Register Addresses.
#define PAGE_CONTROL_REG_ADDR                            0x00
#define SOFTWARE_RESET_REG_ADDR                          0x01
#define CLOCKGENMUXING_REG_ADDR                          0x04
#define PLL_P_AND_R_VAL_REG_ADDR                         0x05
#define PLL_J_VAL_REG_ADDR                               0x06
#define PLL_D_VAL_MSB_REG_ADDR                           0x07
#define PLL_D_VAL_LSB_REG_ADDR                           0x08
#define CODECINTERFACECONTROL_REG_ADDR                   0x1B

#define CODECSECONDERYINTERFACECONTROL_REG_ADDR          0x20

#define NDACVAL_REG_ADDR                                 0x0B
#define MDACVAL_REG_ADDR                                 0x0C
#define DOSR_VAL_MSB_REG_ADDR                            0x0D
#define DOSR_VAL_LSB_REG_ADDR                            0x0E
#define ADC_NADC_VAL_REG_ADDR                            0x12
#define ADC_MADC_VAL_REG_ADDR                            0x13
#define AOSRVAL_REG_ADDR                                 0x14 
#define VOLUMECONTROL_REG_ADDR                           0x74
#define DRCCONTROL1_REG_ADDR                             0x44
#define DACLEFTVOLUMECONTROL_REG_ADDR                    0x41
#define DACRIGHTVOLUMECONTROL_REG_ADDR                   0x42
#define HPOUTPUTDRIVERSPOPREMOVALSETTINGS_REG_ADDR       0x21
#define HEADPHONEDRIVERS_REG_ADDR                        0x1F
#define DACLANDDACROUTPUTMIXERROUTING_REG_ADDR           0x23
#define HPLDRIVER_REG_ADDR                               0x28
#define HPRDRIVER_REG_ADDR                               0x29
#define LEFTANALOGVOLTOHPL_REG_ADDR                      0x24
#define RIGHTANALOGVOLTOHPR_REG_ADDR                     0x25
#define LEFTANALOGVOLTOSPK_RED_ADDR                      0x26
#define MICBIAS_REG_ADDR                                 0x2E
#define DELTASIGMAFINEGAININPUTSELECTION_REG_ADDR        0x30
#define ADCINPUTSELECTIONFORMTERMINAL_REG_ADDR           0x31
#define DACINSTRUCTIONSET_REG_ADDR                       0x3C
#define DACCOEFFICIENTBUFFERCONTROL_REG_ADDR             0x01
#define DACDATAPATHSETUP_REG_ADDR                        0x3F
#define DACVOLUMECONTROL_REG_ADDR                        0x40
#define ADCDIGITALMIC                                    0x51
#define ADCDIGITALVOLUMECONTROLFINEADJUST_REG_ADDR       0x52
#define SPKDRIVER_REG_ADDR1                              0x2A
#define SPKDRIVER_REG_ADDR2                              0x2B
#define CLASSDSPEAKERAMPLIFIER_REG_ADDR                  0x20

// Beep Generator Addresses
#define LEFTBEEPGENERATOR_REG_ADDR                       0x47
#define RIGHTBEEPGENERATOR_REG_ADDR                      0x48
#define BEEPLENGTH_MSB_REG_ADDR                          0x49 
#define BEEPLENGTH_MIDDLEBITS_REG_ADDR                   0x4a 
#define BEEPLENGTH_LSB_REG_ADDR                          0x4b 
#define BEEPSINX_MSB_REG_ADDR                            0x4C
#define BEEPSINX_LSB_REG_ADDR                            0x4D
#define BEEPCOSX_MSB_REG_ADDR                            0x4E
#define BEEPCOSX_LSB_REG_ADDR                            0x4F

// Initial Settings Struct
typedef struct TLV320AIC3100Setting
{
  uint8_t Address;
  uint8_t Page;
  uint8_t Value;
} TLV320AIC3100Settings ;

// The settings array definition and initialization.  - The values are written to the proper registers during the init of the TLV320AIC3100.
static TLV320AIC3100Settings SettingsArr[] = 
{
  /*   Register Address                      |  Register Page   | Value           */
  
  CLOCKGENMUXING_REG_ADDR                    ,      0            , CLK_GEN_MUX_VAL ,  // PLL_clkin = MCLK , codec_clkin = PLL_CLK. Page 0
  PLL_P_AND_R_VAL_REG_ADDR                   ,      0            , PLL_P_AND_R_VAL ,  // PLL enabled, P = 5, R = 2.
  PLL_J_VAL_REG_ADDR                         ,      0            , PLL_J_VAL       ,  // J = 32.   
  PLL_D_VAL_MSB_REG_ADDR                     ,      0            , PLL_D_VAL_MSB   ,  // D = 0.  
  PLL_D_VAL_LSB_REG_ADDR                     ,      0            , PLL_D_VAL_LSB   ,  
  CODECINTERFACECONTROL_REG_ADDR             ,      0            , 0x00            ,  // Mode is i2s , Wordlength is 16, BCLK and WCLK are inputs.  Page 0
                                                                                   
  CODECSECONDERYINTERFACECONTROL_REG_ADDR    ,      0            , 0x00            ,  // Din is fed to cedec serial interface block, DAC and ADC share same WCLK, primary BCLK and WCLK are fed to codec interface, ADC_WCLK is obtained from GPIO1 (TODO: is this correct??).
                                                                                   
  NDACVAL_REG_ADDR                           ,      0            , NDAC_VAL        ,  // NDAC is powered up and set to 4. 
  MDACVAL_REG_ADDR                           ,      0            , MDAC_VAL        ,  // MDAC is powered up and set to 4. 
  ADC_NADC_VAL_REG_ADDR                      ,      0            , NADC_VAL        ,  // ADC NADC divider is powered up , and set to 4.
  ADC_MADC_VAL_REG_ADDR                      ,      0            , MADC_VAL        ,  // ADC MADC divider is powered up , and set to 25.
  AOSRVAL_REG_ADDR                           ,      0            , AOSR_VAL        ,  // AOSR  is set to be 128. Page 0
  DOSR_VAL_MSB_REG_ADDR                      ,      0            , DOSR_MSB_VAL    ,  // DOSR MSB is set to be 0. Page 0
  DOSR_VAL_LSB_REG_ADDR                      ,      0            , DOSR_LSB_VAL    ,  // DOSR LSB is set to be 128. Page 0
  VOLUMECONTROL_REG_ADDR                     ,      0            , 0x00            ,  // Volume control through pin disable. Page 0
  DRCCONTROL1_REG_ADDR                       ,      0            , 0x00            ,  // DRC disable, th and hy. Page 0
  DACLEFTVOLUMECONTROL_REG_ADDR              ,      0            , 0x00            ,  // 0 db gain left. Page 0.
  DACRIGHTVOLUMECONTROL_REG_ADDR             ,      0            , 0x00            ,  // 0 db gain right. Page 0.
  HPOUTPUTDRIVERSPOPREMOVALSETTINGS_REG_ADDR ,      1            , 0x4E            ,  // De-pop, Power on = 800 ms, Step time = 4 ms. Page 1
  HEADPHONEDRIVERS_REG_ADDR                  ,      1            , 0xC6            ,  // HPL and HPR powered up. Page 1 // TODO: changed the val from c2 to c6 because the bit 0 is r only and bit 2 is 1 only.
  DACLANDDACROUTPUTMIXERROUTING_REG_ADDR     ,      1            , 0x44            ,  // LDAC routed to HPL, RDAC routed to HPR. Page 1   // TODO: changed the val from 88(original script value) to 44(actual value on codec sw)
  HPLDRIVER_REG_ADDR                         ,      1            , 0x0E            ,  // HPL - Unmute and gain 1db. Page 1
  HPRDRIVER_REG_ADDR                         ,      1            , 0x0E            ,  // HPR - Unmute and gain 1db. Page 1
  LEFTANALOGVOLTOHPL_REG_ADDR                ,      1            , 0x00            ,  // No attenuation on HP. Page 1
  RIGHTANALOGVOLTOHPR_REG_ADDR               ,      1            , 0x00            ,  // No attenuation on HP. Page 1
  LEFTANALOGVOLTOSPK_RED_ADDR                ,      1            , 0x00            ,
  MICBIAS_REG_ADDR                           ,      1            , 0x0B            ,  // MIC BIAS = AVDD. Page 1
  DELTASIGMAFINEGAININPUTSELECTION_REG_ADDR  ,      1            , 0x40            ,  // MICPGA P = MIC 10k. Page 1
  ADCINPUTSELECTIONFORMTERMINAL_REG_ADDR     ,      1            , 0x40            ,  // MICPGA M - CM 10k. Page 1
  DACINSTRUCTIONSET_REG_ADDR                 ,      0            , 0x19            ,  // Select DAC DSP mode 11.  page 0 // TODO: Original script value = 0x0B
  DACCOEFFICIENTBUFFERCONTROL_REG_ADDR       ,      8            , 0x04            ,  // Enable adaptive filter. Page 8.
  DACDATAPATHSETUP_REG_ADDR                  ,      0            , 0xD6            ,  // POWERUP DAC left and right channels (soft step disable). page 0.
  DACVOLUMECONTROL_REG_ADDR                  ,      0            , 0x00            ,  // UNMUTE DAC left and right channels.page 0.
  ADCDIGITALMIC                              ,      0            , 0x80            ,  // POWERUP ADC channel.page 0.
  ADCDIGITALVOLUMECONTROLFINEADJUST_REG_ADDR ,      0            , 0x00            ,  // UNMUTE ADC channel.page 0.
  SPKDRIVER_REG_ADDR1                        ,      1            , 0x1C            ,  // Unmute Class-D Left.  page 1. // TODO: verify that both sides done in one command (in the script done in two lines).
  SPKDRIVER_REG_ADDR2                        ,      1            , 0x1C            ,  // Unmute Class-D Right. page 1.
  CLASSDSPEAKERAMPLIFIER_REG_ADDR            ,      1            , 0xC6               // Power-up Class-D drivers. page 1. 
};

0 Luis Fernando Rodriguez S. over 8 years ago in reply to Yuri Cherniakov

TI__Guru* 84915 points

Hi, Yuri,

The registers configuration seems to be all in order. Could you try reading the registers flags to ensure that ADC and DAC are configured correctly? Please verify the Page 0 / Registers 37 & 38.

Additionally, could you try using the ADC-to-DAC loopback (Page 0 / Register 29) to verify that ADC and DAC are working correctly? This function routes the ADC output to the DAC input.

Best regards,
Luis Fernando Rodríguez S.

0 Yuri Cherniakov over 8 years ago in reply to Luis Fernando Rodriguez S.

Expert 1740 points

Hi Luis,

I have read the flag registers and here are the results:

from reading the datasheet this seems OK, could you please confirm?

Also, i tried the loop back activation. When i turned it on using the evaluation board i was able to hear

the microphone input contentiously, on my device couldn't hear anything.

0 Luis Fernando Rodriguez S. over 8 years ago in reply to Yuri Cherniakov

TI__Guru* 84915 points

Hi, Yuri,

If the loopback activation was successful, then there should be something wrong with the clock signals. Could you please verify that the clock signals are all in phase and that they respect the clocking times of the datasheet? Additionally, I recommend to verify that the serial data protocol is correct.

Best regards,
Luis Fernando Rodríguez S.

0 Yuri Cherniakov over 8 years ago in reply to Luis Fernando Rodriguez S.

Expert 1740 points

I have went over the registers again and i may have found a mistake (microphone routing and some other differences from the EVM software).
I can currently hear myself speaking to the microphone on the speaker. There are still two problems:

1. The volume of the output is very low and i can hear myself only when the input to the mic is above a certain point. Moreover, it is very noisy (signal wise).

2. When i try to use the HSP demo and let the Din sound on the speaker, nothing happens, though i have routed the Din to the SPK.

3. I have found out that the thermal pad is not connected to analog ground on my device. Can this influence the other problems i have described? (particularly the volume problem).

I have checked the clocks as you said, i made sure that:

- CODEC_CLKIN <= 110MHz

- 512Khz <= PLL_CLKIN/P <= 20MHz

- 80Mhz <= PLL_CLKIN * J.D * R/P <= 110Mhz

- 4 <= R *J <= 259

can you recommend anything else?

0 Luis Fernando Rodriguez S. over 8 years ago in reply to Yuri Cherniakov

TI__Guru* 84915 points

Hi, Yuri,

Have you tried using another ADC/DAC processing block? Some processing blocks have a better performance than others. I recommend to use a different block with Page 0 / Registers 60 - 61.

Please let me know if the problem persists.

Best regards,
Luis Fernando Rodríguez S.

0 Yuri Cherniakov over 8 years ago in reply to Luis Fernando Rodriguez S.

Expert 1740 points

Hi Luis!

I have tried using a different processing block, unfortunately this is not the problem and changing the processing block did not help.

Let me describe the current situation:

- The WCLK and BCLK are defined as inputs for the codec and are generated by the Bluetooth module (cc2564), moreover, i can see both clock functioning during the testing.

- The microphone is connected and functioning as well, loop back works just fine, i can hear my input loud and clear.

- The Din line is also an input received from the Bluetooth module, while observing this line i can see a valid signal. In-spite of that, i can not hear the routed Din in the speaker (although it is functional and tested at the same moment with a microphone).

Please advise on how to continue

0 Luis Fernando Rodriguez S. over 8 years ago in reply to Yuri Cherniakov

TI__Guru* 84915 points

Hi, Yuri,

Could you try additional tests, please?

Could you try using a processing block with an interpolation filter A? Additionally, I saw in your register configuration that you are using the mixer amplifier. Do you have the same results when the HPL/R direct connection is being used? Finally, could you tell me if the HP outputs are completely enabled? Which voltage level you are seeing when the codec is configured?

Best regards,
Luis Fernando Rodríguez S.

0 Yuri Cherniakov over 8 years ago in reply to Luis Fernando Rodriguez S.

Expert 1740 points

Hi Luis!

We have managed to find the problem, we had some mistakes in defining clocking and data word lengths.
The issue was fixed,

thanks for your responses and help!

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TLV320AIC3100 Initialization requierments for BT to SPK output