Other Parts Discussed in Thread: ADS1672
I am working on a new project that uses the ADS1672 ADC and also uses the PCM1690-Q1 DAC. Due to how the ADC works it is possible for me to set up the timing such that I can have the ADC convert the analogue signal at a rate equivalent to 300+ KHz but actually sample the signal at a lower rate (192 KHz in my case) since it only makes one conversion per start pulse. The beauty of this is that it provides me extra time to perform manipulations on the data before the next conversion is performed. It allows what I need done basically in real time. What I would like to know is whether or not I could perform the same type of timing trick with the PCM1690-Q1 DAC. I know that the serial input of the DAC is controlled by the 2 clock signals (BCLK and LRCLK) so transferring the data to the input registers is only contingent on the speed of those clocks. What I am not sure about is how that effects the sampling mode that the unit uses to ensure that the input is a "1" or "0". From the datasheet it seems that the oversampling rate has only certain values and is tied to the system clock. What I would like to be able to do is shift the data into the DAC at a rate equivalent to 300+ KHz but only shift the data in once every 192 thousandth of a second. Does anyone know if what I want to do is even possible? The reason for using the PCM1690-Q1 is that it saves me from having to use 8 single or 4 stereo ADCs. Any and all help is appreciated.
Regards.
