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TLV320DAC3120: DAC channel shutdown sequence

Taku Imaizumi
Prodigy 70 points
Part Number: TLV320DAC3120

Hi, I am using TLV 320 DAC 3120.
Please tell me how to properly shut down the DAC channel.


Below is my processing order.
I referred to the description of 5.7 CLOCK Generation and PLL in the data sheet.
1.Drop the D7 bit of Page 0, Register 63.
2.Polls until the D7 bit of Page 0, Register 37 is dropped.
3.When the D7 bit of Page 0, Register 37 goes down, power down in order of MDAC and NDAC.

However, since the D7 bit of Page 0 Register 37 will not drop, it will continue to poll.
Incidentally, there is a description that the power status flag of D7 bit and D3 bit of Page 0 Register 37 should be read in the document of TLV 320 DAC 3120, but the D 3 bit is a reserved area, is not it?

By the way, I do not use PLL_CLK.

best regards

Taku Imaizumi

  • 0
    TI__Guru** 100965 points
    Hi Imaizumi-san,

    I have verified that flag on Page 0 - Reg 37 - bit D7 is working after I write 0x16 into Page 0 - Reg 63 (D7 turns 0). Have you verified that your write command is working fine? Also please note that registers are MSB first.
    You should read only Page 0 - Reg 37 - bit D7. Bit D3 is a typo, you should not be polling this flag; I think the text was taken from another data sheet most likely from a stereo device where D3 is RDAC and D7 is LDAC.
    However I have also verified that D7 and D3 from Page 0 - Reg 37 should change its state simultaneously. At least the EVM is doing so.

    Best regards,
    -Ivan Salazar
    Audio Applications Engineer - Low Power Audio & Actuators
  • 0 in reply to Ivan Salazar
    Prodigy 70 points
    Hi Ivan-san

    Thank you for your answer.
    After I write 0x16 into Page 0 - Reg 63 , I have verified that flag on Page 0 - Reg 37 - bit D7. But bit D7 does not turn 0.
    However, I understand that my register setting may be okay from your answer.
    After that, I confirmed whether there are problems other than that.
    And I noticed that input MCLK (CODEC_CLKIN)was stopped before powering down the DAC.
    Without stopping input MCLK,I have verified that flag on Page 0 - Reg 37 - bit D7 is working after I write 0x16 into Page 0 - Reg 63 (D7 turns 0).
    Is this that I should not stop the input clock before I power down the DAC?

    Best regards,
    Taku Imaizumi
  • 0 in reply to Taku Imaizumi
    TI__Guru** 100965 points
    Imaizumi-san,

    That is correct. Some internal blocks of these devices need the input clock to work properly.
    You should stop input clock after the power down sequence.

    Best regards,
    -Ivan Salazar
    Audio Applications Engineer - Low Power Audio & Actuators
  • 0 in reply to Ivan Salazar
    Prodigy 70 points
    Hi, Ivan-san

    Thanks for your reply.
    I implement to stop the input clock after the DAC power down sequence.

    Thank you .

    Taku Imaizumi