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PCM5101A: BCK rise time criteria?

KANJI SHIBATANI
Mastermind 6205 points
Part Number: PCM5101A
Other Parts Discussed in Thread: PCM5101

Hello

Would you please adivse about the criteria  which should be kept in PCM5101A  BCK ?

 

Back Ground

My customer had been used PCM5101A for several models of their portable audio recorder from 2012.

Anyway, customer is evaluating their new product (using PCM5101A)  for EMI (emission from their board) test , and they have found rise time of

BCLK should be slower in order to pass EMI test in their board.

 

Question ( please see attached ppt, thank you )

1

Customer just only keep the criteria for tBCY >16ns ,  tBCL > 16ns   in the slas859a table7? 

( page 3 of this document) That is to say, customer use tBCY=162.7ns (BCK=6.144MHz), no need to keep BCK duty=50%?

 

2

We don’t find spec. of rise time and fall time about BCK in the data sheet.  

However, do you have advice ( any criteria ) about  rise/fall time for BCK? 

3

Do you think the DAC output white noise increase is  due to BCK rise time?         

If so, would you advise the any criteria of mamxim rise time for BCK?         

 

4.     

We doubt independent master clock* may be the cause  but no problem if master clock rise time

had been changed.

Also, they had used this scheme from past.   Do you think this should be considered? * http://www.tij.co.jp/jp/lit/an/slaa469/slaa469.pdf

 

Please advise.

Best Regards

PCM5101_BCK rising time vs noise.pptx

  • 0
    TI__Guru 57800 points

    Hi, Shibatani-san,

    Please refer to below comments regarding the questions you provided:

    1/2- The specifications for BCK from the mentioned table are referenced to the case where the maximum frequency of the BCK signal is used (24.576MHz for the PCM5151A). That being said, in general for I²S specification, the maximum rise/fall time allowed should be about 10% of the period of each clock signal, while the high/low time should be about 40%. For a 6.144MHz clock (like BCK in customer's application), rise/fall time  should be less than 16ns and high/low time should be about 65ns.

    3/4- Large BCK rise/fall time might be contributing to the noise problem, however I think that having a separate MCLK signal could be a more important issue. The app note you are describing should be followed, having a separate MCLK might lead to incorrect data reading by the DAC. One thing to mention is that this device is able to operate in 3-wire mode without a MCLK as long as the clock inputs are compliant with the values depicted in Table 11 of the datasheet. I would recommend to connect MCLK to operate the part in Clock Slave with BCK PLL mode and check if the noise issue is improved.

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • 0 in reply to Diego Melendez
    Mastermind 6205 points

    Dear Diego-san,

    Thank you very much for your answer quickly!

    I believe my customer will follow your advice.

    Thank you and best regards