dear all:
I used TAS2505 on the project. The sampling rate is 16K. My configuration is as follows. The sound played by SPK is noisy and the sound quality is not very good. Please help me to see what is wrong with the register configuration？ thank you!
static const unsigned char TxData[] = // Table of data to transmit
{
/// A2DP Sink - Enable Speaker Playback Class-D ///
///////////////// Initialization //////////////////
// Px, P0 Switch to Page 0
0x00, 0x00,
// Software Reset Register
// P0, R1, b0. Reset = SW Reset - Internal Registers
0x01, 0x01,
// Px, P1 Switch to Page 1
0x00, 0x01,
// LDO Control Register
// P1, R2, b5-4. AVDD LDO Output = 1.8V
// P1, R2, b3. PLL and HP Level Shifters = Power Up
0x02, 0x04,
////////////// Digital Configuration //////////////
// Px, P0 Switch to Page 0
0x00, 0x00,
// Clock Setting Register 1 - Multiplexers
// -> PLL_CLK = (PLL_CLKIN x R x J.D)/P
// -> 84.672MHz = (3.528MHz x 1 x 24.0)/1 --> For Fs = 44.1KHz
// -> XX.XXXMHz = (XXXXMHz x X x XX.0)/1 --> For Fs = 48KHz
// P0, R4, b3-2. PLL_CLKIN = BCLK (01)
// P0, R4, b1-0. CODEC_CLKIN = PLL_CLK (11)
0x04, 0x07,
// Clock Setting Register 2 - PLL P and R Values
// P0, R5, b7. PLL = Power Up (1)
// P0, R5, b6-4. PLL Divider P = 1
// P0, R5, b3-0. PLL Divider R = 1
0x05, 0x91,
// Clock Setting Register 3 - PLL J Value
// P0, R6, b5-0. PLL Divider J = 24
0x06, 0x18,
// Clock Setting Register 4 - PLL D Value
// P0, R7, b5-0. (MSB) PLL Divider D = 0
// P0, R8, b7-0. (LSB)
0x07, 0x00,
0x08, 0x00,
// Clock Setting Register 11 - NDAC Values
// P0, R11, b7. NDAC = Power Up
// P0, R11, b6-0. NDAC = 3 (DAC_CLK = CODEC_CLKIN / NDAC)
0x0B, 0x83,
// Clock Setting Register 12 - MDAC Values
// P0, R12, b7. MDAC = Power Up
// P0, R12, b6-0. MDAC = 8 (DAC_MOD_CLK = DAC_CLK / MDAC)
0x0C, 0x88,
// DAC Setting Register 1-2 - DOSR Value
// -> DAC_Fs = CODEC_CLK_IN / (NDAC.MDAC.DOSR)
// -> 44.1KHz = 84.672MHz / (3.8.80)
// -> 48KHz = TBD KHz / (X.X.80) TBD
// -> DOSR MUST be a multiple of 8 - slaa404c.pdf
// -> MDAC * DOSR >= ResourceClass * 32
// -> DOSR = 64, for Low-Power Mode
// -> DOSR = 128, for High-Performance Mode
// P0, R13, b1-0.(MSB) DOSR = 80 (DAC_Fs = DAC_MOD_CLK / DOSR)
// P0, R14, b7-0.(LSB)
0x0D, 0x00,
0x0E, 0x50,
// Audio Interface Setting Register 1 - Configuration
// P0, R27, b7-6. Interface Mode = DSP Mode (01)
// P0, R27, b5-4. Data Length = 16bits (00)
// P0, R27, b3. BCLK = Input (0)
// P0, R27, b2. WCLK = Input (0)
0x1B, 0x00,
// Audio Interface Setting Register 2 - Data Offset
// P0, R28, b7-0. Data Offset = 1
0x1C, 0x01,
// DAC Instruction Set
// Filter A - Best Performance, PRB_P1
// P0, R60, b4-0. Processing Block: PRB_P1
0x3c, 0x01,
////////////// Analog Configuration //////////////
// Px, P1 Switch to Page 1
0x00, 0x01,
// REF, POR and LDO BGAP Control Register
// P1, R1, b4. Master Reference = Power Up
// P1, R1, b3. POR Power Control = Power Up
// P1, R1, b1. LDO Bandgap = Power Up
0x01, 0x10,
// Common Mode Control Register
// P1, R10, b6. Analog Output Common Mode = 0.9V
0x0A, 0x00,
// P1, R3, b5. DAC Mode = Enabled/Low-Power
// P1, R3, b4-2. DAC PTM Control = PTM_P3
0x03, 0x00,
// Speaker Volume Control 1 ?Best value = 0dB
// P1, R46, b6-0. Spk Analog Gain = 0dB
0x2E, 0x00,
// Speaker Volume Control 2 ?Tune to best value
// P1, R48, b6-4. Spk Driver Gain = 12.0dB
0x30, 0x50,
// Speaker Amplifier Control 1
// P1, R45, b1. Spk Driver = Power Up/Reset
0x2D, 0x02,
//////////////////// Power On ///////////////////
// Px, P0 Switch to Page 0
0x00, 0x00,
// DAC Channel Setup Register 1
// P0, R63, b7. DAC Power = Power Up
// P0, R63, b5-4. DAC Path = Mix of L+R
// P0, R63, b1-0. Soft-Step Control = 1 step/WCLK
0x3F, 0xB4,
// DAC Channel Digital Volumer Control Register
// Max Value = 0dB, Min Value = -63dB. Not recommended to use + values
// P0, R65, b7-0. DAC Volume = 0dB (0)
0x41, 0x00,
// DAC Channel Setup Register 2
// P0, R64, b6-4. Auto Mute = Enabled / DC >100 consecutive inputs
// P0, R64, b3. Mute Control = Unmuted
0x40, 0x14
};
