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PCM5100A-Q1: Power Save Modes

Part Number: PCM5100A-Q1

Our customer is facing issue of "No sound output" after Power Save Mode in PLL operation mode.

On datasheet page33 there is description as below.


When expected audio clocks (SCK, BCK, LRCK) are applied to the PCM510xA device, or if BCK and LRCK start

correctly while SCK remains at ground level for 16 successive LRCK periods, the device starts its powerup

sequence automatically.


My concern is if I2S data rate is changed before and after of "Power Save Mode", in that case, PCM510x can automatically re-synchronize and powerup? Or PCM510x will waiting expected rate I2S clock input.


In other word, to re-synchronize to new rate of I2S input, Is Vdd power down reset required?




  • Hello Mochizuki-san,

    Changing the BCLK and LRCK rate after entering power save mode should not cause any issue.  The PLL should be able to acquire new rate.  One caveat to this is that the new rate must also be supported by the PLL.  

    Table 11 shows the supported rates.



  • Paul-san,

    Thank you for the prompt reply.

    End equipment still have no sound issue 3/100 times of occurrence probability at "Power down mode" cycling test.

    We will try to duplicate the phenomena on the EVM.



  • Mochizuki-san,

    Do you have any updates for us on this topic? Thanks.
  • Hi Duke and Paul,
    We have confirmed PLL resynchronization was done without entering Power down reset mode, so it is automatically monitoring LRCK and BCK clock rate after Power save mode. My first question is clear.

    On the end equipment issue was fixed by changing DSP firmware to avoid LRCK burst output after Power save mode.
    We expect there were multiple root causes , SCK pin got switching noise input during LRCK burst timing, then failed to initialize PCM510x PLL.