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TPA3116D2: Trimming the output offset

Part Number: TPA3116D2
Other Parts Discussed in Thread: TPA3122D2, , TPA3123D2

Hi,

Is there a simple way of getting closer to a 50% duty cycle? Its slightly off that a fluke meter can pick up. I am now running in BTL mode, so that did help reduce the offset some. This is referenced to Vcc and ground.

Thanks,

Bryan

  • Hi Byran,
    The output offset has already been trimmed in the factory before releasing to market, so the offset difference between P and N channel should be very small. Besides, considering that the output is in differential mode, the absolute offset actually makes no sense. We just need to pay attention to the offset between P and N channel. Another thing that could affects the output offset is the mismatch between the P and N channel, e.g. inductors and capacitors mismatch in the LC filter. So from the sytem application level, please make sure the mismatch between P&N are good enough.
    Best regards,
    Shawn Zheng
  • Hi Byran,
    Could you please help to close this question if it's answered? Please let us know if you have more question.
    Best regards,
    Shawn Zheng
  • Hi Shawn,

    I tried to trim out the output offset with tweaking the +/- input side but to no avail, I also tried regular and BTL modes, the BTL mode chooses the right channel (offset) to determine offset for that mode. So for every few out of ~ 20 I get close to centered PWM. Any other ways to center the PWM externally? Any other inputs that I can tweak to achieve this?

    Thanks,

    Bryan

  • Hi Bryan,
    May I know what 'regular' means please? Does it mean PBTL mode or SE mode? TPA3116D2 doesn't support SE output mode(TPA3122D2/TPA3123D2 supports SE mode). Applying a DC signal on the input to calibrate the DC offset on the output is not feasible, because the device has AC coupled input and actually doesn't reponse DC input signal to protect the speaker. May I know why you want a very accurate DC offset in the application? For most of the existing application, TPA3116D2 can meet the output DC offset requirement.
    Best regards,
    Shawn Zheng
  • Hi Shawn,

    Sorry my definitions didn't work. Stereo mode vs mono mode is what I was making a comparison to. In stereo mode I was able to alter the outputs +/- 10-100mV without the IC shutting down, the problem was when I got one corrected, the other output would shift in the opposite direction, which was somewhat expected. What would be ideal I think is if I could shift the clock level up or down, that might work. I could discuss the application but that would require a NDA. I'm guessing the device is trimmed at the factory, before or after die packaging?

    Thanks,

    Bryan

  • Hi Bryan,
    Thank for the info. I agree with that your experiment result is expected. DC detection is related to input/ouput dc voltage and gain setting. We have a document that introduces this feature. www.ti.com/.../sloa261.pdf
    Generally all of the trim operations are done after packaging. From the device itself, there is no other option to adapt the output dc offset. Maybe you could try to shift the output voltage outside the device.
    Best regards,
    Shawn Zheng