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SRC4193: understanding the automatic sample rate detection

Part Number: SRC4193

Dear TI E2E members,

i would like to use this IC in a prototype DAC project, but i am having a hard time understanding the automatic sample rate detection. Let's say i have a 24bit I2S signal with a 32bit frame, coming from a USB to I2S converter. The Fs can be 44.1, 48, 88.2, 96, 176.4, and 192kHz. What i need is a constant 192kHz 20bit left justified signal, no matter what the input frequency is. This is where this IC would come in, but the automatic sample rate detection is confusing me. If i select the 20bit left justified output, how can i set the 192kHz? Is it defined by the input reference clock, or the BCKO in slave mode? If so, do i have to calculate the clock speed like this: 192000 * 2 * 32, or like this: 192000 * 2 * 20?

  • Hi, welcome to e2e forum.

    As far as tth SRC4193 goes, the LRCKI (pin 6) is an input pin if the device is configured as SLAVE. This clock rate is equal to fs, the input sampling frequency. IFMT[2:0] bits in Control Register 3 are used to select the data format.

    Similarly, LRCKO (pin 24) is configured as input pin when the device is configured as SLAVE. This clock rate is equal to fs, the output sampling frequency. OFMT[2:0] and OWL[1:0] bits of Control Register 3 are used to select the data format and word length for the output port.

    This allows you to set the 192kHz/20-bit LJ format for the output. Hope this clarifies your question to use SRC4193 to use in your application. Thanks.

    Best regards,
    Ravi

  • Dear Ravi,

    so, if i understand it correctly, i will need a reference clock that has 192000 * 2 * 20 (7.68MHz) frequency, and feed this LRCKO to the SRC in slave mode.

  • Yes, this should allow you to use the SRC4193 to achieve the 192kHz/20-bit output. Please let us know if you need any additional help and we will be glad to assist.

    Best regards,
    Ravi
  • Dear Ravi,

    my next question is: can i use this IC to convert a 24bit I2S audio signal that has a 32 bit wide frame, to a 20 bit LJ signal with a 20 bit frame, while not changing the sample rate?

  • As far as the SRC4193 goes, it can definitely handle the above requirements. All you need to do is configure the IFMT[2:0] to '001' (24-bit I2S) and OFMT[1:0] to '00' (Left-justified) & OWL[1:0] to '01' (20-bit) and you will have achieved the results.

    Would you be interested in alternative device that can achieve the same? or you happen to have SRC4193 in your solution already?

    Best regards,
    Ravi