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TAS5717: Output Power vs THD+N in PBTL mode

Will Liu
Intellectual 2360 points
Part Number: TAS5717

Hi folks,

Do we have Output Power vs THD+N graph of TAS5717/9 in PBTL mode?

The impedance of load is 4ohm.

Do you have TSA5717/9 reference schematic in PBTL mode?

Thank you.

Sincerely,

Will Liu

  • 0
    TI__Mastermind 24835 points
    Hi Will,
    I think you can use the BTL mode data in the same case(PVDD, Load, input frequency). it would be very similar for PBTL mode. In PBTL mode, the output current is divides into two halves, it actually decrease the current in each channel and then improve the thermal performance. But it doesn't improve the linearity range much.
    In PBTL mode, the PBTL pin needs to be driven to High level. And the output OUTA after LC filter and OUTB after LC fitler are combined. The same is OUTC and OUTD. Please find more info in our TAS5717 EVM user's guide for PBTL mode config: www.ti.com/.../slos655a.pdf
    Best regards,
    Shawn Zheng
  • 0 in reply to Shawn Zheng
    TI__Intellectual 2360 points

    Hi Shawn,

    Your link is TAS5717 datasheet.

    Do you mean page 17 in TAS5717 Use guide?

    It's not clear for PBTL schematic.

    User guide mentions:

    "JP1 on the daughter card is for PBTL select. Jumper IN means non-PBTL mode. For PBTL, remove this

    jumper." 

    JP1 is 3-pin jumper, what does Jumper IN mean? If it's removed, there is no pull-high connection. Which pin is PBTL pin?

    Thank you.

    Sincerely,

    Will Liu

  • 0 in reply to Will Liu
    TI__Mastermind 24835 points

    Hi Will,

    I appologize for the confusion. It is a typo in the document, please ingore that description. The following picture shows the PBTL connection. Short OUT_A and OUT_B after the LC filter, short OUT_C and OUT_D after LC filter. Connect the load between them. Make sure the register 0x25 is set to 0x01  10  32  45 for PBTL mode. 

    Best regards,

    Shawn Zheng