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PCM4222: Resolution of each pin of a stereo channel and I2S COM sequence

Rinaldi Segecin
Prodigy 40 points
Part Number: PCM4222

I'd like to know if each pin from a stereo channel input pair (VIN) with 2.8Vpp has 24 bits of resolution and not the whole channel 5.6Vpp and if it's that true the size of payload data from a sample in the left justified communication would have 48/64 bits for every channel or the I2S protocol alternates from what pin the payload data is coming from (both of this cases are illustrated bellow).

or

  • 0
    TI__Expert 5645 points

    Hi Rinaldi,

    Welcome to e2e community!

    Let me clarify few things wrt Left Justified (LJ) & TDM mode. As you may already know, the I2S and LJ formats support two channels of audio output data & TDM data formats can support up to eight channels of audio output data on a single data line.

    To add more details wrt both modes, let's look at each in Master & Slave mode as well -

    I2S and LJ data formats -
    In Master Mode, the BCK clock output rate is fixed in Master mode, with the Normal mode being 128fS and Double & Quad Speed modes being 64fS.

    In Slave Mode, BCK clock input rate of 64fS or 128fS is recommended for Normal mode, while 64fS is recommended for Double & Quad Rate modes.

    TDM data formats -
    BCK rate depends upon the sampling mode for either Slave or Master operation. For Normal sampling, the BCK must be 256fS. Double Speed mode requires 128fS, while Quad Speed mode requires 64fS. This requirement limits the maximum number of channels carried by the TDM formats to eight for Normal mode, four for Double Rate mode, and two for Quad Rate mode.

    FMT1[pin 43] /FMT0[pin44] will dictate the mode (TDM/LJ/I2S) and SUB1[pin25] /SUB0[pin26] will dictate sub-frame assignment. 

    Hope this clarifies your question regarding payload data.


    Best regards,
    Ravi

  • 0 in reply to Ravi Patil
    Prodigy 40 points

    Thank you for your reply Ravi, I was actually more concerned about the resolution per pin per channel. But I've just realize that I was mistakenly thinking of Vp not Vpp that would degrade the ADC a lot. Resolution of 24 bits i'ts for the whole channel and 0 to 5.6V correlates to a value with 24bits of resolution. 

    Thank you again.