Other Parts Discussed in Thread: DIT4192,
Do we have any application notes on how to drive the master clock pin of the SRC4197?
Do you have a check list that would help to make sure that the proper clocks were chosen?
There really are no pictures of the master clock, thus the questions.
The data sheet on the SCR4194EVM adds this:
The DIT4192 transmitters (U7 and U17) have additional configuration switches, summarized in Table 3−4 and Table 3−5. For the clock divider, the corresponding control pins need to be set dependent upon the incoming master clock (MCLK) and output sampling rates, fSout.
The master clock (MCLK) rate is set by either reference clock RCKIA or RCKIB, or by the corresponding DIT CLOCK input at connector J4 or J9 (dependent upon the clock configuration; see Figure 3−3 and Figure 3−4).
Please send additional information so that I can help my customer set up the master clock to the SCR4194 correctly.
Thanks for your help with this!
Richard Elmquist
