This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

SRC4184: Bit clock in slave mode

Part Number: SRC4184

In slave mode, the SRC4184 is configured as an input pin and operates at rates from 32fs to 128fs.

What would happen if we provide a bit clock that is 256fs?

Are there alternative parts that would be more appropriate for the 256fs bit clock?

Thanks.

  • Hi Gregory,

    As far as the SRC4184 design goes, we have have a counter that will overflow if BCK is 256fs and hence the range supported for BCK is 32fs to 128fs. The other SRCs also have similar implementation and hence we will run into data being corrupted (especially if you are configuring the device to Right-justified mode) when BCK is 256fs.

    I assume you are getting the BCK from host processor in your system. Is there any chance we can divide that clock before the SRC device? 

    Thanks & Best regards,
    Ravi