Hi,
MCLK is 12.288MHz and i want that ADC_FS is set at 48kHz
So i disable PLL and CLOCK-GEN Muxing is set to MCLK.
%NADC: 1
%MADC:4
%AOSR:64
ADC_FS is then 48000Hz
ADC_INTF_CTRL_2: is set to ADC_CLK(12.288MHz)
%N: 2
BCLK: 6.144MHz (I thought that 32bit x 2 Channels x 48000Hz x 2 )
Is BCLK correct? And how should i set the DOUT register?
EDIT: I measured the PINS and BCLK is 6.144MHz, WCLK is 48kHz and DOUT is 48kHz
Shouldnt DOUT be 6.144MHz too?
