• State TI Thinks Resolved
  • Locked Locked
  • Replies 4 replies
  • Answers 1 answer
  • Subscribers 30 subscribers
  • Views 818 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

SRC4382: SRC4382 Bypass ASRC

SRC4382: SRC4382 Bypass ASRC

Bret Wang
Prodigy 10 points
Part Number: SRC4382

Hi Sir 

     My Application is re-sampling audio input(I2S) from Port A(32kHz~96kHz) to Port B(fixed in 48KHz) .

     and set register like below

     0x3  <= 8'b00000000

     0x4  <= 8'b00000011

     0x5 <= 8'b00011000

     0x6 <=  8'b00000011

     and MCK(pin 25) input is 12.288Mhz 

            48kHZ Audio(by i2S)  pass to Port A interface , but no any output from Port B signal . and make sure the input(Port A) audio signal is correct . 

     Is there something wrong?  or I forgot something 

Bret Wang (王炫煇)

NCG/FPGA, Advantech Co., Ltd.

Tel: +886.2.2792.7818 Ext.1242  

  • 0
    Guru 11785 points

    Hi Sirs,

    Sorry for pushed, have any update on this ??

    Thanks!!

  • 0 in reply to Shu-Cheng LIN
    Guru 11785 points

    Hi Sirs,

    Sorry for pushed, have any update on this ??

    Thanks!!

  • 0 in reply to Shu-Cheng LIN
    TI__Expert 5645 points
    Hi Shu-Cheng,
    I'm currently looking at this and would also like to request additional details in order to help w the complete configuration -
    - Is Port A and Port B in SLAVE mode or MASTER mode?
    - Do you have MCLK as master clock source for audio serial port?

    Best regards,
    Ravi
  • 0
    TI__Expert 5645 points

    Hi Bret,

    Apologies for the late reply as I did not get notified about the post for some reason.

    I have made some assumption wrt Port A and Port B being in SLAVE mode.  With that in consideration, below is the signal routing in the device -

    Below is the set of register writes that will achieve the same -

    Register         Value

    0x03               0x01       #Port A Output Data Source=Port A; Mode=SLAVE; Format = I2S

    0x04               0x00       

    0x05               0x31      #Port B Output Data Source=SRC; Mode=SLAVE; Format=I2S

    0x06               0x00

    0x2D              0x00      #SRC input source=Port A; Clock Source=MCK

    Please feel free to change the script if you are planning to use the audio serial ports in MASTER mode. 

    Thanks & Best regards,
    Ravi