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PCM4204: Reading samples in slave mode

Part Number: PCM4204

I am designing an acquisition system using the PCM4204.  I will be running the 4204 in slave mode from a FPGA.  The FPGA will input the SCKI clock and derive the BCK and LRCLK from that.  I am going to use quad rate, left-justified PCM format. 

My question is how does the FPGA kno when the samples are available to clock out?

Since the FPGA is creating the BCK and LRCLK, if it asserts LRCLK high and starts clocking data out the SDOUT1/2 pins, how does it kno that it is getting a full 24-bit sample?

Walk me through how this chip works:  The ADC part comes up with 4 24-bit samples.  It has to transfer these to a serial output register.  Then the external hardware (the FPGA) has to clock out 64-bits to read the 4 values before the next set of samples are ready.  What keeps the guts of the 4204 from loading the serial registers during a shift-out operation?  Also, what happens to the 4 samples if the FPGA clocks nothing out?  Or clocks the data out too slow?

Thanks,
Ed

  • Hi Ed,
    Welcome to e2e forum.

    On Power-up, the internal reset signal is forced low resulting in the device being in RESET state. All the supply rails are monitored and once we are above the required threshold, we release the internal reset signal and wait for the SCKI input. Once we detect SCKI input, the device initialization requires ~1024 SCK cycles before we enable to SDOUT1 and SDOUT2. As far as FPGA being able to detect the samples present, you will have to detect the edge on the SDOUTx outputs once the BCK/LRCK are enabled.

    For ex: when in 24 bit I2S format, the data will be MSB first and delayed from LRCK by one bit, then 24 bits of data and rest of the LRCK channel frame will be ignored. The number of bits in your LRCK frame will depend on your BCK clock. If your BCK is 64*Fs, then you have 64 bits per LRCK, or 32 bits per channel, that means 1 ignored bit to start, 24 bits of data, and 8 ignored bits, then the start of the next 24 bits of data. BCK should be a multiple of the sampling frequency.

    Thanks.

    Best regards,
    Ravi

  • Ravi,

    Thanks for the response.  This doesnt directly answer my question but is very informative.

    In your first paragraph, you are alluding to the fact that the SDOUTx lines will be low if there are no samples to read out.  Is that true?

    Since there is no "data ready" signal, I am trying to understand how the 4204 works inside.  If I assert LRCK high and bring BCK low, figure 3(a) suggests the MSB of a sample will be driven on the SDOUTn lines.  Does this sound correct?  I am beginning to think the 4204 uses the edge of the LRCK to load (or enable) the output shift register.

    Another thing I noticed is that the audio serial port clock signals have an 'I' appended to them in figure 3, I assume this means they are inputs (slave mode)?

    Ed

  • Hi Ed,t
    You are correct...SDOUTx are forced LOW until the device goes through initialization sequence and output is enabled only after the device comes out of this sequence.

    I do realize that PCM42xx devices do not have DATA READY output pin which we do have on some other family of ADC/interface/Codec devices. As far as you interpretation of Fig 3(a) goes, it is correct interpretation for Left-justified format and the other examples are also provided for RJ and I2S formats.

    And the 'I' definitely related to Input clocks for SLAVE mode but it is true for MASTER mode where the clocks will be outputs. Thanks.

    Best regards,
    Ravi