I am designing an acquisition system using the PCM4204. I will be running the 4204 in slave mode from a FPGA. The FPGA will input the SCKI clock and derive the BCK and LRCLK from that. I am going to use quad rate, left-justified PCM format.
My question is how does the FPGA kno when the samples are available to clock out?
Since the FPGA is creating the BCK and LRCLK, if it asserts LRCLK high and starts clocking data out the SDOUT1/2 pins, how does it kno that it is getting a full 24-bit sample?
Walk me through how this chip works: The ADC part comes up with 4 24-bit samples. It has to transfer these to a serial output register. Then the external hardware (the FPGA) has to clock out 64-bits to read the 4 values before the next set of samples are ready. What keeps the guts of the 4204 from loading the serial registers during a shift-out operation? Also, what happens to the 4 samples if the FPGA clocks nothing out? Or clocks the data out too slow?
Thanks,
Ed