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TAS5755M: Question of TAS5755 MCLK and BCLK Signal Integrity

Wayne Chen (ex FAE)
Guru 15950 points
Part Number: TAS5755M

Hi Sirs,

According to the TAS5755 specification, the Rise/fall time for SCLK/LRCLK spec =MAX 8ns, customer's SOC's WS: Rise = 15.83 Fall = 14.08 SCK: Rise = 25.44ns Fall = 26.08ns which are over TAS5755's specifications.



However, the I2S specification defined the SCLK/LRCK's rise time is 60ns max. Would you pls advise a reasonable numbers for customer to follow up?

Addition, would you please assist us to review if customer's MCLK waveform compliant with TAS5755's design?






Thank you and Best regards,

Wayne Chen
11/27/2018

 

 

  • 0
    TI__Mastermind 24835 points
    Hi Wayne,
    The spec in the datasheet is for the max acceptable clock frequency, so it's a little strict for most of the application. According to our previous experience, the rise/fall edge should be faster than 10% of the clock period. Another important thing you need to pay highly attention to is the clock signal integrity. Make sure the clock trace is not too long and the impedance matching is good. Any glitch on the clock edge could cause the performance issue.
    Best regards,
    Shawn Zheng