Hi Sirs,
Would you please assist us to review the below block diagram if it can support customer's input clock schemes properly?
1. I2S BCLK = 1.536MHz, I2S LRCLK = 48KHz
2A. I2S BCLK = 1.4112MHz, I2S LRCLK = 441.KHz
2B. I2S BCLK = 1.536MHz, I2S LRCLK = 48KHz
2C. I2S BCLK = 1.12MHz, I2S LRCLK = 35.2KHz
3A. I2S BCLK = 1.536MHz, I2S LRCLK = 48KHz
3B. I2S BCLK = 1.4112MHz, I2S LRCLK = 44.1KHz
Thank you and Bet regards,
Wayne Chen
12/27/2018