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SRC4392: SRC4392

Part Number: SRC4392
Other Parts Discussed in Thread: MSP430FR5849


I am working on a design using two SRC4392 devices in an audio tester device.

In order to test the host MCU software controlling the SRC4392 devices I am using a SRC4392EVM.

Communication between RSC's and the host MCU is via SPI.

I want to use the SRC output attenuation capability (registers0x30 and 0x31) to vary the output attenuation on the fly.

After initialization the device works as expected but if I change the output attenuation there is no change in the output amplitude until I restart the device with the new register 0x30 / 0x31 values. Then the attenuation change takes effect.

Are the SRC attenuation values not updated real time but only set at initialization of the device or do I miss a command to effectuate the output attenuation change?

If attenuation values are not updated real time do I need to write the new attenuation values, reset the SRC and take it out of reset again using register 0x01?

The the device also has to re-sync which is not my preference. I only want to change the volume attenuation.

  • Hi,

    I am using at startup a bulk write of all 51 registers using the auto-increment feature.

    After some tests I found out that re writing all 51 registers with only different values in the left and right channel attenuation registers the output volume can be adjusted, no reset or SRC powerdown needed.

    Does this means that for every register change I have to re-write all 51 registers in order to take effect?

  • Hi, Jan,

    Sorry for the delayed response. My Colleague in charge of this device is out f the office this week. I have notified about your questions, so he can respond early next week once he comes back from the Holiday break.

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • Hi Jan,

    Happy New Year...sorry for the delay as I was OoO for the holidays.

    Regarding the attenuation registers, the values can be changed during the operation and this should result in volume adjustment during the run-time. This should not require all 51 registers to be re-written. The one thing that I can recommend is to toggle the PDSRC bit of Register 0x01 after the attenuation registers are configured. I'll check w the design team and also run some tests on the EVM on my end to confirm the same, but you can check if this results in the expected behavior wrt output volume when the registers are poked...Thanks.

    Best regards,


  • Hi Ravi,
    I'll be waiting for the reply then.
    I found another behaviour I cannot figure out.
    When I change the input - output frequency ratio of the SRC, the value of the SRC ratio readback registers stays at 0x0F, 0xFF.
    I'd expect them to change with changing ratio's.
    Besides that, is there also a formula available that describes what the integer and fractional parts should be at certain ratio's or putting it differently, what is the notation for the fractional part?
  • Hi Ravi,

    I tried the SRCPD toggle after writing the left and right attenuation registers.

    It works but not reliably. After a number of consecutive changes the SRC won't start and I have to do a complete power cycle to get it working again.

    I'll stick to do a burst write of all 51 registers since that hasn't caused the SRC to hang sofar.

    I also figured out the problem with the SRC ratio register readback.

    In my register read function, I also do a bulk read of all 51 registers in one go but I released the chip select line immediately after initiating the last read, in stead of letting the SPI finish that last read.

    I have to do some more tests but I get now different values when programming different ratio's.

    I am still curious however to interpret the values, especially the fractional part.

    Regards  Jan

  • Hi Ravi,

    I slightly modified my SPI transmit and receive routines to allow for a variable number of bytes to be transmitted or received. Everything works fine now. writing left and right attenuation registers and reading the SRC ratio registers individually.

    For receive I test on the MSP430FR5849 SPI  busy flag rather than the receive interrupt flag. This ensures a complete receipt before initiating the next SPI write with zero to generate the required signals to the SRC4392 SPI port to read out the next register.

    Thanks for the support

  • Hi Jan,

    Thanks for the update and we are glad the issue is resolved and please do not hesitate to contact us on any future support needed on any of TI chipsets.

    Best regards,