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TPA3255: Slave PWM frame sync; how is this achieved?

dB
Prodigy 60 points
Part Number: TPA3255

G'Day

We're designing an audio amp with multiple (4) TPA3255-Q1 devices. The (3) slaves will be sync'ed from the master.

We observe the (differential) oscillator/clock emitted from the master, Fosc is 6x the PWM frame rate, Fpwm. Each Fosc cycle therefore represents 1/6 of the PWM period or 60º. Fpwm would appear to be derived from Fosc via a divide by 6. 

Referring to Table 7 in the datasheet (SLASEM8A) "Master/Slave Inter Channel Delay Settings" the Slave 1 delay is 60º, representing one Fosc period.  

There does not appear to be a means (well, I can't find one) to sync the (internal) master PWM frame to the slaves, lest there be a 6:1 ambiguity of the slave PWM phase!

Q1.  Are the slaves PWM frame somehow sync'ed to the master by some magic?

Q2. If the slaves PWM frames are not in sync with the master can a random multiple of 60º be expected after RESET?

Regards

David

  • 0
    TI__Genius 9140 points
    David,

    We are in China public holiday now, I will feedback you when back to office this sunday.

    Dylan
  • 0 in reply to Dylan Yao
    TI__Genius 9140 points
    David,

    I need to understand more about your questions.

    "We observe the (differential) oscillator/clock emitted from the master, Fosc is 6x the PWM frame rate". Are you saying you see a radiation of 6th harmonic of PWM frequency? Is it measured by a near-field probe or in EMI chamber? How about the other harmonics, like 3rd and 5th harmonic?

    "There does not appear to be a means (well, I can't find one) to sync the (internal) master PWM frame to the slaves, lest there be a 6:1 ambiguity of the slave PWM phase!" Are you saying there is no way to sync them? In fact, it is designed inside the device, there is a clock tree to do this.

    As to your questions:
    Q1. Are the slaves PWM frame somehow sync'ed to the master by some magic?
    Not any magic. As described in datasheet, if set in slave mode, the PWM will be synced with OSC_IO pin input clock. there is some clock tree inside to do that.

    Q2. If the slaves PWM frames are not in sync with the master can a random multiple of 60º be expected after RESET?
    If not synced with a master, is that OSC_IO clock comes from another oscillater? If not synced, that means they are radom, not any phase relationship.



    Dylan