TAS2552: does TAS2552 support Ratio Rates of 32

Shu-Cheng LIN

Guru 11785 points

Part Number: TAS2552
Other Parts Discussed in Thread: TAS2562

Hi Sirs,

Sorry to bother you.

We would like to know does TAS2552 support Ratio Rates of 32?

If not does TI have others solution can suggest it?

Because our table shown for SBCLK to FSYNC ratios,

1.1.536M/48K = 32
2. 3.072M/48k = 64
3.512k/16k = 32

But from datasheet didn't show support Ratio Rates of 32.

over 4 years ago

0 Luis Fernando Rodriguez S. over 4 years ago

TI__Guru* 84915 points

Hi, Shu-Cheng,

The TAS2552 does support the 32 bit rate. It actually can be configured with register 0x05 / bits 0-1 (word length):

www.ti.com/.../tas2552.pdf

Could you provide the datasheet where you found the information of table 17, please? The datasheet in ti.com doesn't have the table 17.

Best regards,
Luis Fernando Rodríguez S.

0 Shu-Cheng LIN over 4 years ago in reply to Luis Fernando Rodriguez S.

Guru 11785 points

Hi Sirs,

Thanks for your reply.

The table 17 and 18 are from TAS2562 which we are first survey parts, not TAS2552.

That's why we to ask spec on TAS2552.

Sorry for let you confuse.

0 Luis Fernando Rodriguez S. over 4 years ago in reply to Shu-Cheng LIN

TI__Guru* 84915 points

Hi, Shu-Cheng,

Thank you for your clarification.

Please let me know if you have additional comments or questions on this. We will be glad to help you.

Best regards,
Luis Fernando Rodríguez S.

0 Colin_Gu over 4 years ago in reply to Luis Fernando Rodriguez S.

Prodigy 180 points

Hi Team,

what we need is that does 2552 support below table but not only Bit rate.

Bit Clock	Frame sync	Bit Rate
1.536 MHZ	48 KHZ	16 bps
3.072 MHZ	48 KHZ	32 bps
512 KHZ	16 KHZ	16 bps
512 KHZ	16 KHZ	32 bps

0 Luis Fernando Rodriguez S. over 4 years ago in reply to Colin_Gu

TI__Guru* 84915 points

Hi, Jianbo,

There's no problem. The TAS2552 supports these clocks frequencies. I just recommend to ensure that the clocks respect the recommended times of tables 6 and 7 ( www.ti.com/.../tas2552.pdf ).

Best regards,
Luis Fernando Rodríguez S.

0 Colin_Gu over 4 years ago in reply to Luis Fernando Rodriguez S.

Prodigy 180 points

Hi Team,

Thanks a lot!

1. Update above table for typo issue and pls help to check/verify.

Bit Clock	Frame sync	Bit Rate
1.536 MHZ	48 KHZ	16 bps
3.072 MHZ	48 KHZ	32 bps
512 KHZ	16 KHZ	16 bps
1.024 MHZ	16 KHZ	32 bps

2. For our current HW design TAS2552 will be used for speaker function only and is it possible to provide register setting directly based on below audio format as we don't want to establish another alsa device.

a. 1.536Mhz & 48Khz & 16 bps for music

1). SND_SOC_DAIFMT_I2S /* I2S mode */

2). SND_SOC_DAIFMT_CBS_CFS /* codec clk & FRM slave */

3). SND_SOC_DAIFMT_NB_NF /* normal bit clock + frame */

4). SND_SOC_DAIFMT_CONT /* continuous clock */

b. 512Khz & 16Khz & 16 bps for voice

1). SND_SOC_DAIFMT_I2S /* I2S mode */

2). SND_SOC_DAIFMT_CBS_CFS /* codec clk & FRM slave */

3). SND_SOC_DAIFMT_NB_NF /* normal bit clock + frame */

4). SND_SOC_DAIFMT_CONT /* continuous clock */

c. audio volume ctrl.

0 Luis Fernando Rodriguez S. over 4 years ago in reply to Colin_Gu

TI__Guru* 84915 points

Hi, Jianbo,

There's no problem, the corrected value is also supported by this device.

In all our audio devices with I2S protocol, the most important thing is to respect the rising and falling times as specified in the datasheet. Any clock ratio between the BCLK and WCLK (frame sync clock) will be always accepted if they are multiple of 16, 20 or 24 bits. All the clock rates that you shown above respect this ratio and there shouldn't be any issue on this.

Best regards,
Luis Fernando Rodríguez S.

0 Colin_Gu over 4 years ago in reply to Luis Fernando Rodriguez S.

Prodigy 180 points

Hi Team,
Thanks and could u help to check below?
===
For our current HW design TAS2552 will be used for speaker function only and is it possible to provide register setting directly based on below audio format as we don't want to establish another alsa device.

a. 1.536Mhz & 48Khz & 16 bps for music

1). SND_SOC_DAIFMT_I2S /* I2S mode */

2). SND_SOC_DAIFMT_CBS_CFS /* codec clk & FRM slave */

3). SND_SOC_DAIFMT_NB_NF /* normal bit clock + frame */

4). SND_SOC_DAIFMT_CONT /* continuous clock */

b. 512Khz & 16Khz & 16 bps for voice

1). SND_SOC_DAIFMT_I2S /* I2S mode */

2). SND_SOC_DAIFMT_CBS_CFS /* codec clk & FRM slave */

3). SND_SOC_DAIFMT_NB_NF /* normal bit clock + frame */

4). SND_SOC_DAIFMT_CONT /* continuous clock */

c. audio volume ctrl.
===

0 Luis Fernando Rodriguez S. over 4 years ago in reply to Colin_Gu

TI__Guru* 84915 points

Hi, Jianbo,

Could you provide more details on this? Are you looking for a registers configuration for cases a, b and c? Is my understanding correct? If so, we would need of additional features that you are looking into your application in order to provide a correct registers configuration.

Best regards,
Luis Fernando Rodríguez S.

0 Colin_Gu over 4 years ago in reply to Luis Fernando Rodriguez S.

Prodigy 180 points

Hi Team,
Are you looking for a registers configuration for cases a, b and c? Is my understanding correct?
=> Yes.
If so, we would need of additional features that you are looking into your application in order to provide a correct registers configuration.
=> 1. as i said before for 2552 we only have speaker function but do not need mic.
2. play music file with 48K sample rate & 1.536Mhz(Or 3.072Mhz) BCLK & 16(or 32) bit rate
3. voice call with 16k sample rate & 512K(Or 1.024Mhz) BCLK & 16(or 32) bit rate
4. I2S format
===
SND_SOC_DAIFMT_I2S /* I2S mode */
SND_SOC_DAIFMT_CBS_CFS /* codec clk & FRM slave */
SND_SOC_DAIFMT_NB_NF /* normal bit clock + frame */
SND_SOC_DAIFMT_CONT /* continuous clock */
===
That's all we need now and if further information is needed pls tell me.thanks.

0 Colin_Gu over 4 years ago in reply to Luis Fernando Rodriguez S.

Prodigy 180 points

Hi Team,
Any update?Thanks.

0 Shu-Cheng LIN over 4 years ago in reply to Luis Fernando Rodriguez S.

Guru 11785 points

Hi Sirs,
Sorry for pushed, have any update on this case?
Thanks!!

0 Luis Fernando Rodriguez S. over 4 years ago in reply to Shu-Cheng LIN

TI__Guru* 84915 points

Jianbo, Shu-Cheng,

Please find attached the registers configuration that could be useful for the features that you mentioned.

Registers Configuration Example.txt

# 32-bit 64-fs
# Slave Reg Value
w 80 01 12
w 80 08 10
w 80 02 EA
w 80 03 5D
w 80 04 00
w 80 05 13
w 80 06 00
w 80 07 C8
w 80 09 00
w 80 0A 00
w 80 12 15
w 80 14 0F
w 80 01 10

It is in format: w 80 xx yy

w - write
80 - I2C address
xx - register address
yy - register data

This code should work for all the features except the point #3 (16KHz). In order to change from 48KHz to 16KHz, it would be necessary to modify the register 3 (bits 2-0). These bits select the WCLK frequency to be used. So, when 48KHz is used, the value should be 5D. When 16KHz is used, it should be configured as 5A.

Please let me know if you have additional questions or comments on this.

Best regards,
Luis Fernando Rodríguez S.

0 Colin_Gu over 4 years ago in reply to Luis Fernando Rodriguez S.

Prodigy 180 points

Hi Team,

Thanks for the update and does these register setting include init part of tas2552?

0 Luis Fernando Rodriguez S. over 4 years ago in reply to Colin_Gu

TI__Guru* 84915 points

Hi, Jianbo,

Yes, this is the registers configuration for the TAS2552. I particularly suggest to verify each register of the sequence to check if it coincides with what you are looking for.

Please take a look at it and let me know if you have questions or comments.

Best regards,
Luis Fernando Rodríguez S.

0 Colin_Gu over 4 years ago in reply to Luis Fernando Rodriguez S.

Prodigy 180 points

Hi Team,
Got it,thanks and i'll verify it after device coming out.

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TAS2552: does TAS2552 support Ratio Rates of 32