DIT4096: Power sequence of DIT4096

There is not a specified power-supply sequence for the DIT4096 but make sure you don't violate any of the maximum ratings in the datasheet.

Datasheet Page 6 Section "Reset and Power-Down Operation" describes the mandatory reset sequence that must be used. I've copied the information below.

The DIT4096 includes a reset input, RST (pin 15), which is
used to force a reset sequence. When the DIT4096 is first
powered up, the user must assert RST low, in order to start
the reset sequence. The RST input must be low for a minimum
of 500ns. The RST input is then forced high to enable
normal operation. For software mode, the reset sequence will
force all internal registers to their default settings. In addition,
the reset sequence will force all channel status bits to 0 in
Software mode.
While the RST input is low, the transmitter outputs,
TX– (pin 17) and TX+ (pin 18), are forced to ground.
Upon setting RST high, the TX– and TX+ outputs will remain
low until the rising edge of the SYNC clock is detected at
pin 12. Once this occurs, the TX– and TX+ outputs will
become active and be driven by the output of the AES-3
encoder.
In Software mode, the DIT4096 also includes software reset
and power-down bits, located in control register 02H. The
software reset bit, RST, and the software power-down bit,
PDN, are both active high.