I use the codec IC with I2S audio interface.for the ADC - IN3 and DAC - LOL and ROL.
the IC is initialized as secondary I2S slave with BCLK and WCLK provided to the codec by the host controller of the codec.
the ADC_CLK is provided by the inserted BCLK (500KHz) and the PLL that multiply the BCLK by 4 (2MHz) to provide the ADC_CLK, instead of the MCLK (as was with the Evaluation board).
I saw that the DI and DO of the secondary I2S of the codec including the BCLK and WCLK (8KHz) are as expected.
I insert a signal to left ADC and right ADC and I could see the sampled data 16 bit of each channel seems to be properly and as expected but when we sent data (even constant data) we could not see the analog signal on the DACs LOL and ROL output as refer to the sent data. All we could see on the DACs output was noise (seems to be random) with amplitudes that were even reach the maximum allowed amplitude.
As told we don't use and not insert MCLK to the codec.
the question is what we are missing so the DACs LOL and ROL analog signal output is not according the data that is sent to the DACs (via DIN) and instead we receive large noise?
Is the inserted BCLK of the I2S is a sufficient CLK signal in order to enable also the DACs to work according the data that is sent from the I2S?
If required I can send the registers init values as configuration via the I2C interface.
Thanks,
Kobi