• State TI Thinks Resolved
  • Locked Locked
  • Replies 4 replies
  • Answers 1 answer
  • Subscribers 30 subscribers
  • Views 483 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TLV320AIC3268: Difference in Output Sound Quality with Difference in MCLK Frequency Value

Anthony Yoo68
Expert 1320 points
Part Number: TLV320AIC3268

Hi!

We are testing DIGITAL(I2S) TO DIGITAL(I2S) MIX using two TLV320AIC3268 EVMs.

If we set PLL CLK = MCLK and MCLK = 11.3MHZ in EVM's DEFAULT setting, the audio quality will sound very good.
However, I changed the PLL CLK = MCLK, MCLK = 2.82Mhz, and changed the PLL settings as shown in the table below in the datasheet.


However, the resolution of the audio quality is lower than that of 11.3Mhz.
Does the higher the frequency of the PLL CLK, the better the sound quality?

Thank you.

Best Regards.

From Anthony.

  • 0
    TI__Mastermind 30100 points

    Anthony, 

    No, The frequency of the PLL input should not have any effect on the sound quality.  When you say the sound quality is lower, do you have some measurements to show that the sound quality is lower?

    Also confirm your settings, and make sure that you have it programmed correctly in both cases.   You could also share the two configurations that you used and I could see if I could see what was going on. 

    best regards,

    -STeve Wilson

  • 0 in reply to Steve-Wilson
    Expert 1320 points

    Hi! Steve

    Unfortunately, due to time and equipment conditions, we do not have comparable data for sound quality.

    But it's clear that it's a big difference.

    Of course, my settings may be wrong.

    So we share about PLL Clokc configuration.

  • 0 in reply to Anthony Yoo68
    Expert 1320 points

    Hi~!!

    Gentle reminder!!

    Please check it.

    Thank you.

    Best Regards!

    From Anthony

  • 0 in reply to Anthony Yoo68
    TI__Mastermind 30100 points

    Anthony, 

    for the 11.289Mhz PLL_IN clock settings your MADC is set to 8,  making the DSP clock 45.12Mhz, while the other has the MADC set to 3. making the DSP clock = 16.92Mhz.  The issue could be related to the processing requirements of the processing block.  ie the processing block needs more DSP cycles than the Current clock allows for. 

    Try swapping the NADC/MADC settings in the PLL_IN = 2.82Mhz.  So that MADC = 5 and NADC = 3.  This would give you a DSP CLOCK of 28.2Mhz. 

    That will give you more DSP cycles.  While the DSP clock rates are still not identical,  I think the increase should resolve the issue. 

    best regards,

    -Steve Wilson