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Original question:

SRC4392: DIR locks on 48 kHz and 96 kHz inputs, not 44.1 kHz or 88.2 kHz

SRC4392: Not working - issue with DIR?

Petr Gratz1
Prodigy 30 points
Part Number: SRC4392

Dear sirs,

I have SRC4392 configured as follows:

- spdif input signal 96kHz

- DIR routed to PORTA

- PORTA  24 bit, 96 kHz

- MCLK 24.576 MHz

- BCK and LRCLK as output from PORTA

Checked PORTA output signal with scope:

- LRCLCK ok - 96kHz

- BCK ok - 6.144 MHz

- DATA  - no output ( low)

Registers:

03 - 29h

04 - 01h

0D - 09h

0E - 00h

0F - 22h

10 - 00h

11 - 00h

01 - 3Fh - power on all

I have also checked /LOCK pin and it is high - seems PLL is not locking? What can be wrong?

One other thing I found out - when I try to read registers everything is ok and they are properely set. However when  try to read register 01 instead of getting previously set valhe of 3Fh I’m getting 00h and it seems that other registers are set to default state - 00. Can this be somehow linked to issue mentioned above and reason why I can’t get output from PORTA? Or is register 01 not readable? (Maybe when I try to read from reg 01 it forces Reset somehow?)

  • 0
    TI__Mastermind 30030 points

    Petr, 

    We're a little short handed right now and are working to catch up. 

    I will take a look at this and get back to you today or tomorrow. 

    best regards,

    -Steve Wilson

  • 0 in reply to Steve-Wilson
    Prodigy 30 points

    Tank you Steve. Looking forward for any feedbak or guidance.

    As decribed in my original post the flow is SPDIF on RX2 —> DIR —> PORTA as master. MCLK 24.576 MHz. Input SPDIF signal looks ok, output LRCLK 96kHz and BCK from PORTA as well.  SDOUTA is zero (no signal...) and LOCK is high.

    Any idea what can be wrong? How can I check whether DIR is working properly?

  • 0 in reply to Petr Gratz1
    Prodigy 30 points

    Checked two more things:

    1. Input SPDIF signal 400 mV peak-peak, frequency ok - 64 * 96 kHz

    2. Masked interrupts in registers 16 - 24h and 18 20h and while reading register 14 I’m gettin 04h - DIR lock error. However VBIT showing 0 - valid audio data

    Any feedback or help would be much appreciated

  • 0 in reply to Petr Gratz1
    Prodigy 20 points

    Any feedback please?

  • 0 in reply to Petr Gratz
    Genius 3945 points

    I looked at my SRC4392 configuration.

    The first register I load is 0x7F, the page-select register. That gets set to 0x00, because all of the registers of interest are on that page. It would seem unnecessary to load it with 0x00, but example code I found somewhere did exactly that.

    Reading from register 0x01 should be fine and have no side-effects.

    That the locked signal stays high is a clue -- the DIR is not configured. That your register read backs all result in 0x00 is another clue saying the same.

    Are you using the SPI or I2C configuration interface?