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PCM4222: Need to synchronize multiple devices

DG47
Prodigy 40 points
Part Number: PCM4222

I need to synchronize a significant number of these devices for a multi-channel application.  The power-up sequence must be staged (cannot be powered-on simultaneously) because they draw too much current while performing their reset vs. while operating normally in my application.  Has anyone reset and synchronized a large number of these devices? 

For example: I would like to release 10 at a time from reset and synchronize them with the ones that are currently operating.

  • 0
    Genius 3945 points

    The RST pin on this converters functions as a power-down control. When asserted low, the chip is held in reset and will draw minimal current when the clocks driving it are low (not toggling).

    You don't state what else you have in your system to do the control. You could tie the reset pins of each chip in a group of ten together. Eight pins on a micro controller or FPGA can control 80 converters. You will also need to hold the clock inputs low, so perhaps some kind of gate also controlled by those resets is good.

    A clock tree for a "large number of devices," especially the modulator clock, could be a challenge.

    The synchronization is fairly easy. As long as the converters are in slave mode and the clock inputs to them are identical, they will be synchronized.

  • 0 in reply to Andy Peters
    Prodigy 40 points

    Thanks for your reply,

    The reset, MCLK, LRCLK, and BCLK all have their own clock buffer trees that are controlled using an FPGA.  The delays in the buffer trees are managed by dividing the architecture into banks.  The only way we have been able to synchronize the phases of all the ADCs is to release them from reset simultaneously, which causes a large current draw.  

    You said that synchronizing these devices is easy.  If I wanted to synchronize 80 of these devices, releasing 10 at a time from reset, could I do this if I manipulate the clocks? What would that look like?  Would they all need MCLK (even the ones in reset) but I hold-off on LRCLK and BCLK?  

    There's no information that documents the internal sampling and digitizing this device is performing.  Our experience has shown us that if we do not release these devices from reset simultaneously that the phases are not aligned, which means that the internal analog sampling is occurring at a  different time, even if all the external clock signals are aligned.  

  • 0 in reply to DG47
    TI__Mastermind 30210 points

    DG47, 

    Typically we don't see a need to synchronize so many of these ADCs at once, there is no phase compensation on these devices.  My suggestion would be to release the reset, but not provide an MCLK,  Then once all devices are out of reset, provide the MCLK to all devices simultaneously.  

    you would still need to compensate on your end as the devices do not have any facility for that. 

    best regards,

    -Steve Wilson

  • 0 in reply to Steve-Wilson
    Prodigy 40 points

     

    Thanks Steve,

    I can try what you recommend on the current design to see if it works. Just out of curiosity, how does the synchronization work when using TI development boards in Master and Slave mode? I was going to scope the Master/Slave mode interaction but it would be even better if TI has it documented.

    My initial problem is a large current draw when pulling these devices out of reset simultaneously (while providing MCLK). Will your solution avoid this large inrush? I believe that this inrush is also undocumented by TI. Do you agree?

    You mention not needing to synchronize so many of these devices and there being no phase compensation. Do you have another device of comparable performance that are being synchronized in a large number of channels and/or does contain phase compensation?