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TLV320DAC3120: TLV320DAC3120 generate Beep

Lin Ken HY
Intellectual 310 points
Part Number: TLV320DAC3120

Hi,

I need to let TLV320DAC3120 generate Beep, But i try it for two days.it still output any sound.

I can use i2c to r/w register. and soc no input WCLK,BCLK ,MCLK to this TLV320DAC3120.

first question : Can TLV320DAC3120 generate clock by itself? i read TLV320DAC3120's datasheet,i think it can.

second question : If it can,How can i configure register and generate Beep?

thank you.

  • 0
    TI__Guru* 84915 points

    Hi, Lin,

    I'm taking a look at this. I will provide an answer as soon as possible.

    Best regards,

    Luis Fernando Rodríguez S.

  • 0 in reply to Luis Fernando Rodriguez S.
    TI__Guru* 84915 points

    Lin,

    First of all, welcome to E2E and thank you for your interest in our products!

    Could you provide your circuit schematic in order to have a better approach to this issue?

    The TLV320DAC3120 is capable to generate the WCLK and BCLK, but you would need to configure the device in master mode and provide a valid MCLK.

    Then, in order to generate the beep from the beep generator block, you would need to select the processing block PRB_P25, this is the only block which supports the beep generation. Once the WCLK and BLCK are generated, the processing block will be initialized and you will be able to generate the beep with the configuration that you need.

    I attached a registers configuration example with the TLV320DAC3120 configured in master mode and the beep generator sending a 2KHz tone for 2 seconds.

    The configuration format is w (I2C write command) 30 (I2C address) xx (register address in hex format) yy (register data in hex format)

    DAC3120_Master_Mode_Beep_Generator.txt 
    ###############################################
# Software Reset
###############################################
#
# Select Page 0
w 30 00 00
#
# Initialize the device through software reset
w 30 01 01
#
###############################################

###############################################
# Clock and Interface Settings
# ---------------------------------------------
# The codec receives: MCLK = 11.2896 MHz,
# It generates BLCK = 2.8224 MHz, WCLK = 44.1 kHz
###############################################
#
# Select Page 0
w 30 00 00
#
# PLL_clkin = MCLK, codec_clkin = PLL_CLK,
# PLL on, P=1, R=1, J=8, D=0000
w 30 04 03 91 08 00 00
#
# NDAC = 2, MDAC = 8, dividers powered on
w 30 0b 82 88
#
# DOSR = 128
w 30 0D 00 80
#
# Master mode configured, I2S mode selected
w 30 1b 0c
#
# BCLK source = DAC_MOD_CLK (5.6448MHz)
w 30 1d 05
#
# BCLK N_VAL enabled (BCLK N = 2; BCLK = 5.6448MHz / 2)
w 30 1e 82
#
###############################################

###############################################
# Signal Processing Settings
###############################################
#
# Select Page 0
w 30 00 00
#
# PRB_P25
w 30 3c 19
#
# Enable Adaptive Filtering
w 30 00 08
w 30 01 04
#
###############################################

##########################################
# Configure Class-D Output
##########################################
#
# Switch to Page 1
w 30 00 01
#
# CM = 1.65V
w 30 1f 14
#
# Unmute Class-D (6dB)
w 30 2a 04
# Unmute Class-D (12dB)
# w 30 2a 0c
# Unmute Class-D (18dB)
# w 30 2a 14
# Unmute Class-D (24dB)
# w 30 2a 1c
#
# Power-up Class-D driver
w 30 20 86
#
# Route Analog Volume Control to Class-D Driver, 0dB
w 30 26 80
#
##########################################

##########################################
# Configure HP Output
##########################################
#
# Switch to Page 1
w 30 00 01
#
# De-pop, Power on = 800 ms, Step time = 4 ms
w 30 21 4e
#
# Route Analog Volume Control to HP Driver, 0dB
w 30 24 80
#
# HP output powered up, current limit
w 30 1f 84
#
# HP unmute and gain 0db
w 30 28 06
#
##########################################

##########################################
# Configure DAC Channel
##########################################
#
# Switch to Page 1
w 30 00 01
#
# DAC routed to Mixer Amplifier
w 30 23 40
#
# Switch to Page 0
w 30 00 00
#
# Powerup DAC, DAC => LI2S, soft-step disable
w 30 3f 96
#
# Unmute DAC, 0dB
w 30 40 04 00
#
##########################################

##########################################
# Beep Generator Configuration
##########################################
#
# Go to page 0
w 30 00 00
#
# Writing Beep length to registers 73,74,75 and 30 being the Codec address.
w 30 49 01 
#
# 73 = 49 in hex and so on.
w 30 4A 77
#
# Now writing Sine and cosine coefficients MSB first then LSB in 76,77,78,79
w 30 4B 00
w 30 4C 23
w 30 4D FB 
w 30 4E 7A
w 30 4F D7
#
# Making gain of left channel -2dB and turning on the beep.
w 30 47 84

    I also recommend to take a look at this document for more details about the beep generation.

    http://www.tij.co.jp/jp/lit/an/slaa446/slaa446.pdf

    Please let me know if you have questions or comments on this. We will be glad to help you.

    Best regards,
    Luis Fernando Rodríguez S.

  • 0 in reply to Luis Fernando Rodriguez S.
    Intellectual 310 points

    really really thank you for your help~