• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 30 subscribers
  • Views 313 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TLV320AIC3262: tone generator disappears when adding iDSP_A_D_1

Eggz
Intellectual 365 points
Part Number: TLV320AIC3262


Hello TI,

We have an AIC3262 on a custom board, where we are working to get the connected PDM mic's to work - so far without success - but firstly:

We made a simple script simply adding a tone generator, which works fine. However, when we add an iDSP_A_D_1 to the script the tone generator stops working. There is nothing connected to the iDSP_A_D_1. See below. Any suggestions what is going on? Thanks. 

  • 0
    TI__Expert 6440 points

    Hi Egil,

    The input/output ports should ideally not be left floating. Input ports should be connected to a Coef-to-Data component and output ports to a Data-to-Coef component.

    But the behavior that you describe would not be caused by floating nodes. Have you turned off the Tone Generator in between builds by any chance?

    It does not happen on my end. Please share your process flow and I shall investigate.

    Best Regards.

  • 0 in reply to Diljith
    Intellectual 365 points

    Hi Diljith,
    Thanks for the quick response. We still experience this odd behaviour, see process flow below:

    We hear silence in L channel and an invalid sound like a "grasshopper" in R channel.
    If we remove L channel lines (with the interprocessor), the R channel tone generator works fine.
    Any suggestions?
    Thanks.
    Egil

    aic3262.zip

  • 0 in reply to Eggz
    TI__Expert 6440 points

    Hi Egil,

    The issue is with the clock tree configuration. While configuring the clock tree we should set the DAC DSP Clock such that it has enough cycles to completely process one sample of data before the next one arrives.

    The number of DSP cycles required to process one sample of data is available from the resources panel in PPS.

    For proper operation the DSP Clock should meet this requirement, i.e.

    DSP Clock >=  Sampling Rate * number of DSP Cycles per sample.

    The DSP clock is derived from ADC or DAC input clock and then dividing it by NADC/NDAC.

    In this particular case, with DAC clock input at 4.096 MHz and NDAC at 1, we have about 4096/16 = 256 cycles per sample, which is not sufficient to meet the resource requirements of the process flow (which is closer to ~300). You will probably notice that the tone quality is not that great even with iDSP removed. 

    So, either you need to reduce the DSP processing or increase the DSP clock. Switching to a mono interpolator will lower the resource requirement. To increase DSP clock, you can use the PLL and PLL output can be used as input to DAC and ADC.

    Using PPS's default clock tree the process flow works properly. I have attached it here for reference. The only change I have made is to use the default system settings code.

    Best Regards.

    aic3262_evm.zip