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TAS5733L: what's the Maximum output voltage for TAS5733L.

GW
Intellectual 1880 points
Part Number: TAS5733L
Other Parts Discussed in Thread: TAS5805M

Hi, Team

If i set the input signal to 0dBFS, and set all the others block function to 0dB, such as AGL, Volume, EQ.

what's the Maximum output voltage for TAS5733L(suppose PVDD is larger enough)? 

For the latest device such as TAS5805M, i known it should be 29.5V( suppose PVDD is larger than 29.5V). But i didn't know for TAS5733L.

Thanks.

  • 0
    TI__Expert 6720 points

    Hi GW,


    Compared TAS5805M closed-loop fixed analog gain, TAS5733L is open loop structure, which does not have fix analog gain.

    The 0dBFS of TAS5733L output is the current PVDD value.

    Regards,
    Matthew

  • 0 in reply to Matthew Miao
    TI__Intellectual 1880 points

    Hi,Matthew

    Thanks your response.

    For tuning aspect about open loop device, do you have any documents which could share to me?i just have the TAS5733L EVM user guide http://www.ti.com/lit/ug/slou439/slou439.pdf, but it seems didn't show more detail about open loop turning. in my lab test, it seems the TAS5733L  output not only relate to the PVDD, but also relate to the speaker impedance. i want to known the  exactly relation ship about the output vs PVDD, speaker impedance.

    Thanks.

  • 0 in reply to GW
    TI__Genius 17537 points

    Hi GW, 

    Although not for the TAS57xx family you might find this general tuning guide helpful. 

    Additionally, open loop architecture have an output duty cycle that is equal to the input duty cycle. Since the duty cycle does not change to compensate for changes in supply voltage, the output voltage (and power) change with supply voltage changes.

    In contrast, closed loop architecture, 2nd order feedback loop varies the PWM output duty cycle with changes in the supply voltage. This ensures that the output voltage (and output power) remain the same over transitions in power supply. 

    The relation to the impedance is best modeled in our LC filter calculator tool and the corresponding application report. 

    All the best, 

    Carolina

  • 0 in reply to Caro Walter
    TI__Intellectual 1880 points

    Hi, Carolina

    Thanks your comments and material, I think it's very useful.

    but I just wan to double confirm with you relate to the "input duty cycle". Does it means the I2S input duty cycle?

    for example, if the I2S input signal is -6dBFS, since 20*Lg0.5=-6dB,does it means the input duty is 50%, and output duty is 50%?

    Thanks.

  • 0 in reply to GW
    TI__Genius 17537 points

    Hi GW, 

    Yes I am referring to the I2S input duty cycle. 

    All the best, 

    Carolina

  • 0 in reply to GW
    TI__Expert 6720 points

    Hi GW,

    PVDD is the idle max output voltage, but you need to consider Rdson + output load voltage divider. So different load might have various max output voltage.

    Regards,
    Matthew

  • 0 in reply to Caro Walter
    TI__Intellectual 1880 points

    Hi, Carolina, Matthew

    Thanks your comments.