TLV320ADC3140: MCLK_FREQ_SEL_MODE bit missing in datasheet

user6209000

Hi,

I am trying to setup the TLV320ADC3140 in master I2S mode, and are having some issues getting the clock setup right. I have a 12.88MHz clock source coming into GPIO1 as the MCLK source and have set this frequency in the MCLK_FREQ_SEL field. Here it is stated that this setting is valid if MCLK_FREQ_SEL_MODE = 0 - but this is the only reference to MCLK_FREQ_SEL_MODE in the datasheet.

Observed output with my settings (not setting MCLK_FREQ_SEL_MODE) is a ~1.7Mhz BCLK with a ~6.7 kHz FS (256 ratio, not 64 as configured in the registers).

As the configuring for master mode appnote still not appears to be available, could you please help me with a working setup for the following mode:

- 12.88MHz input on GPIO1

- 48kHz sampling rate, FS/BCLK ratio of 64

- 16 bit I2S output

- Channel 1 and 2 as L/R in I2S stream

over 6 years ago

0 Steve-Wilson over 6 years ago

TI__Mastermind 30230 points

User,

if you are using the EVM, make sure to remove R2 and connect MCLK directly to J13, OR just move R2 to the open R3 position and make sure that the jump is off of J13.

Next please note that there clocks for I2S in master mode do not adhere to the I2S spec. essentially the Fsync edge is synced with the rising edge of BCLK, and as such everything gets shifted left 1 half cycle. There is a workaround. detailed below

BLCK_PL (P0,R7,D[2]) = 1

TX_Edge (P0_R7_D[1])= 1

ASI_FORMAT (P0_R7_D[7:6]) = 2'b10 (LJF)

FSYNC_POL (P0,R7,D[3]) = 1

in other words register 7 should be 0x87

#configure GPIO1 as MCLKinput ** note if you are using the EVM you must also provide MC

configure all other registers, and enable the ADCs

best regards,

-Steve Wilson

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TLV320ADC3140: MCLK_FREQ_SEL_MODE bit missing in datasheet