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PCM1774: Clocking question

Part Number: PCM1774


my customer uses PCM1774 and has the following questions:


PCM1774 is used associated with a Silicon Lab CP2114.


The CP2114 generates 3 clocks to the PCM1774.

-          One clock MCLK at 12MHz connected to the input SCKI of the PCM1774

-          One clock SCK at 48MHz/14=3.428MHz connected to the input BCK of the PCM1774

-          One clock LRCK at 12MHz/250=48kHz connected to the input LRCK of the PCM1774


What is the good setting for the register @ 0x55 ? (NPR[5:0] register).


We set this register to 0x04h (00 0100).

Is it the good setting for this register ?


In the PCM1774 what is called the sampling rate ?


Kind regards,


  • Hi Marion,

    An SCK divider of 250 is not supported by the PCM1774.  I have seen this problem with the CP2114 before.  They will need to use the external MCLK option for the CP2114 to provide the ~49MHz clock to generate a SCLK of fs×256 or an external 48MHz clock to generate the 12MHz USB clock.

    There I recall that a few posts have been made on the SiLabs forum about this as well.