PCM1681: PCM1681 SCK LRCK/BCK timing limitation

Kazuki Kuramochi

Part Number: PCM1681

Hi expert,

I asked SCK LRCK/BCK timiing requirement in this thread previously.
I have question regarding above thread.

In in-phase case, SCK’s rising edge will appear 128 time normally. However if we consider about worst case from jitter, it has possibility of occurring 127 case and 129 case.
I'd like to know whether there is some concern under the above worst case.

Would you tell me it?

Best regards,
Kazuki Kuramochi

over 4 years ago

0 Paul_Frost over 4 years ago

TI__Guru 53563 points

Hi Kuramochi-san,

If the clocks are out of synchronization for 3 LRCK cycles, there is be a clock error and the device will stop playback and try to resynchronize. The occasional single error should not cause a problem.

Thanks,

Paul

0 Kazuki Kuramochi over 4 years ago in reply to Paul_Frost

TI__Genius 9445 points

Hi Paul-san,

Sorry for continue this thread but I have question.

Data sheet said "at least 3-it clock cycle". Is it meant 2 time of BCK error on 1 cycle of LRCK acceptable?
In other words, I'm assuming as follow.

128 pulse SCK => 127 pulse SCK => 129 pulse SCK => 128 pulse SCK : It is not error
128 pulse SCK => 127 pulse SCK => 129 pulse SCK => 129 pulse SCK => 128 pulse SCK : It will stop operation after then recover automatically.

Also, Is there any concern when occurred auto recovery?

Thank you and best regards,
Kazuki Kuramochi

0 Paul_Frost over 4 years ago in reply to Kazuki Kuramochi

TI__Guru 53563 points

Hi Muramochi-san,

You are correct: case 1 does not result in an error, case 2 will result in an error.

The resynchronization can result in an audible click noise.

Thanks,

Paul

0 Kazuki Kuramochi over 4 years ago in reply to Paul_Frost

TI__Genius 9445 points

Hi Paul-san,

I appreciate you swift support.
I understand.

Thank you and best regards,
Kazuki Kuramochi

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PCM1681: PCM1681 SCK LRCK/BCK timing limitation