TAS2110EVM: TDM clock error and Critical ERROR REG[0x2] = 0x2

Hi, Henri,

We will take a look at this thread and will answer as soon as possible.

Best regards,
Luis Fernando Rodríguez S.

Hi Henri,

Did you already read back register 0x24 and identified TDM error from bit 2?

What is the status of the I2S bus when you initialize the device?
The device requires valid I2S signals at the digital input to operate correctly.

Best regards,
-Ivan Salazar
Applications Engineer - Low Power Audio & Actuators

Hi Ivan,

I found the problem. There is a wrong BCLK clock.

I Have :

BCLK = 48 KHz

WLKC = 48KHz

I think WLCK is OK but not BCLK. The tas2110 is a slave device or a master ?

I have to configure BCLK on the tas2110 (which register ?) or with the IMX processor ?

Best regards,

PINEAU Henri

Hi Henri,

BCLK and WCLK cannot be the same frequency, is this a typo?

TAS2110 is slave device, regarding BCLK and WCLK you need to set the ratio between these signal frequencies, eg. BCLK = 12.288MHz and WCLK = 48kHz, then ratio is 256. The capture below is from a different device GUI, but the Playback menu is the same for TAS2110.

Best regards,
-Ivan Salazar
Applications Engineer - Low Power Audio & Actuator

Hi Ivan,

I understand, but it's my processor thatgenerate the BCLK and WCLK. So, why this ratio changed the BCLK Frequency ?

This parameter is just for the slave (tas2110) to understand the ratio between BCLK and WCLK ?

Best regards,

PINEAU Henri

Henri,

I understand BCLK and WCLK is generated by the processor, TAS2110 is the slave device.
However as mentioned the ratio between BCLK and WCLK cannot be 1, BCLK frequency must be higher than WCLK. This parameter must match the frequencies of these signals sent from the processor.

Best regards,
-Ivan Salazar
Applications Engineer - Low Power Audio & Actuator