TLV320AIC3106: reg 102 /page 0: PLL Clock Divider N Value

Bruno Scherrer

Part Number: TLV320AIC3106
Other Parts Discussed in Thread: REG102

Thanks for your reply,

Actually I have another question concerning register 102 / page 0 : Bits D3:0 are ment for configuring a clock divider but I do not know where it is located in the clock generation path, and even not sure it really exists...

In the TLVAIC3106 data sheet - page 22 - Figure 20 (Audio clock generation processing), there is mention of a fixed 1/8 divider in the pll path.

Is reg102 / Bits D3:0 connected somehow to this divider?

The thing is: I've tried different values (i.e dividers) but without seeing any change in the FS clock...

Regards,

Bruno

over 3 years ago

0 Aaron Estrada over 3 years ago

TI__Mastermind 22950 points

Hello Bruno,

Nice catch! This certainly looks like a data sheet error to me. I took a look at the AIC3104 data sheet as the PLL in these two devices are extremely similar ( main difference being the use of GPIO in PLL for AIC3106), and saw that these bits are reserved in the AIC3104. Let me get some clarification on this.

Regards,

Aaron

0 Aaron Estrada over 3 years ago in reply to Aaron Estrada

TI__Mastermind 22950 points

Hello Bruno,

I was wrong and this is actually not a data sheet error at all! This N value is used to generate the CLKOUT on GPIO 1. This is why when changing this value, you did not see a change in Fs. See the image below:

Hope this helps!

Regards,

Aaron

0 Bruno Scherrer over 3 years ago in reply to Aaron Estrada

Intellectual 810 points

Thanks a lot Aaron, it helps indeed...

Regards,

Bruno

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TLV320AIC3106: reg 102 /page 0: PLL Clock Divider N Value