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PUREPATH-CMBEVM: Multi channel decoding via optical input

Jon Hart
Prodigy 200 points
Part Number: PUREPATH-CMBEVM
Other Parts Discussed in Thread: TIDA-060026, TAS5825M, TAS5720M

The TIDA-060026 (TAS5825EVM-SB) shows a multi channel prototype setup where the PPC-MB is connected to one unit, then I2C and I2S are daisy chained to provide amp channels for all the various 9.1 outputs. This means that the PPC-MB must be receiving a multi channel audio stream. Typically this would be encoded information (Dolby or DTS), but I don't believe that the PPC-MB can decode this information. So with this in mind, I have 2 questions:

1. How are the 9.1 channels input into the PPC-MB

2. How are the channels then assigned to the various channels of the downstream modules (assuming they have individual I2C addresses).

  • 0
    TI__Expert 6720 points

    Hi Jon,

    TIDA-060026  (TAS5825EVM-SB) is scalable to 5.1, 7.1 and 9.1 channel configurations, and it's just used to show 2.1 configuration demo.

    As for the capability of multiple channel audio interface with PPCMB, it could use PSIA input with TDM modes for multiple channels selection. Then configure on-board TAS5825M / TAS5720M to select desired output channel.

    Regards,
    Matthew

  • 0 in reply to Matthew Miao
    Prodigy 200 points

    Matthew,

    This makes sense. So what would be the correct registry settings for an 8 channel TDM line operating at 48kHz / 24.576 MHz MCLK / 12.288MHz BCLK (24 bit)? Let's assume we're pulling left and right for the TAS5825 from channels 3 and 4 in the TDM data stream.

    Thanks,

    Jon

  • 0 in reply to Jon Hart
    TI__Intellectual 2430 points

    Hi Jon,

                Assume that:

                1. Your TDM doesn't have offset bit.

                2. Your FS/LRCLK only has one bit pulse.(If your LRCLK >8 bit, need set bit 3-2 of Register 33 to 00)

               You need set Register 0x33/ 0x34 as below:

              0x33 is set to 0x16 (TDM/DSP format for TAS5825M; LRCLK pulse< 8 SCLK; 32bit word_length)

              0x34 is set to 0x40 (64 bit shift for acquire channel 3 and 4)