Other Parts Discussed in Thread: TLV320AIC34, TLV320AIC33
Hi guys,
I am working on TLV320AIC34 evaluation board and I need to test the audio serial data. The codec will work with a DSP in the system that I am developing, but right now unfortunately I have no DSP to talk to.I am searching only to see the output on serial data work in TDM because I need the two block of the codec to communicate on the same interface, so the aim of my test is two obtain two output signal working together in TDM. I read some of the application notes regarding this topic, but I have some problems.
I don't know how to set register 8 D7-D6 for the two codec blocks, I read 256 clock transfer mode is available only for device acting as a master, but if I try to set the blocks or one of the two as master the BCLK and WCLK don't work well anymore and I cannot see good signals on the DOUT pins. Furthermore the outputs does not seem to be high impedance when non valid data are sent, even if I set D5 in register 8. I don't know if my problem is the registers configuration, the hardware configuration of jumpers or switches on the eval board or if maybe I cannot test this situation without the DSP (I only need to see the codec outputs I don't need a response from the DSP). Do you have any advice?
If you have a piece of code working in TDM on the evaluation board will be perfect anyway, I don't care which are the inputs or outputs I only need to assess audio serial data functioning properly.
This is my code.
i i2cfast
w 30 00 00
w 32 00 00
w 30 01 80
w 32 01 80
#reg13:left-DAC data path plays left-channel input data
w 30 0D 80
w 32 0D 80
#reg8:place DOUT in high impedance state when valid data is not being sent and master mode
w 30 08 E0
w 32 08 E0
#reg9:audio serial data in DSP mode with 256-clock transfer mode
w 30 09 48
w 32 09 48
#reg10:introduce offset of 14 bit clocks
w 32 0A 0E
#reg15:left-ADC PGA not muted, gain=4dB
w 30 0F 08
w 32 0F 08
#reg19:LINE1L in single-ended mode, input level control gain=0dB, left-ADC channel powered up
w 30 13 04
w 32 13 04
#reg37:left DAC is powered up
w 30 25 80
w 32 25 80
#reg41:left-DAC output selects DAC_L2
w 30 29 80
w 32 29 80
#reg46:PGA_L routed to HPLOUT
w 30 2E 80
w 32 2E 80
#reg51:HPLOUT output control level=0dB, not muted, fully powered up
w 30 33 0D
w 32 33 0D