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TLV320AIC34EVM-K: TDM communication

Part Number: TLV320AIC34EVM-K
Other Parts Discussed in Thread: TLV320AIC34, TLV320AIC33

Hi guys,

I am working on TLV320AIC34 evaluation board and I need to test the audio serial data. The codec will work with a DSP in the system that I am developing, but right now unfortunately I have no DSP to talk to.I am searching only to see the output on serial data work in TDM because I need the two block of the codec to communicate on the same interface, so the aim of my test is two obtain two output signal working together in TDM. I read some of the application notes regarding this topic, but I have some problems.

I don't know how to set register 8 D7-D6 for the two codec blocks, I read 256 clock transfer mode is available only for device acting as a master, but if I try to set the blocks or one of the two as master the BCLK and WCLK don't work well anymore and I cannot see good signals on the DOUT pins. Furthermore the outputs does not seem to be high impedance when non valid data are sent, even if I set D5 in register 8. I don't know if my problem is the registers configuration, the hardware configuration of jumpers or switches on the eval board or if maybe I cannot test this situation without the DSP (I only need to see the codec outputs I don't need a response from the DSP). Do you have any advice?

If you have a piece of code working in TDM on the evaluation board will be perfect anyway, I don't care which are the inputs or outputs I only need to assess audio serial data functioning properly.

This is my code.

i i2cfast
w 30 00 00
w 32 00 00
w 30 01 80
w 32 01 80
#reg13:left-DAC data path plays left-channel input data
w 30 0D 80
w 32 0D 80
#reg8:place DOUT in high impedance state when valid data is not being sent and master mode
w 30 08 E0
w 32 08 E0
#reg9:audio serial data in DSP mode with 256-clock transfer mode
w 30 09 48
w 32 09 48
#reg10:introduce offset of 14 bit clocks
w 32 0A 0E
#reg15:left-ADC PGA not muted, gain=4dB
w 30 0F 08 
w 32 0F 08
#reg19:LINE1L in single-ended mode, input level control gain=0dB, left-ADC channel powered up
w 30 13 04
w 32 13 04
#reg37:left DAC is powered up
w 30 25 80
w 32 25 80
#reg41:left-DAC output selects DAC_L2
w 30 29 80
w 32 29 80
#reg46:PGA_L routed to HPLOUT
w 30 2E 80
w 32 2E 80
#reg51:HPLOUT output control level=0dB, not muted, fully powered up
w 30 33 0D
w 32 33 0D

  • Hi,

    I have followed the tutorial in application note "SLAA301". I have switched off SW2-4 and I have copied and modified the register configuration written in the document, since in my case I will use only two codecs (the two blocks inside TLV320AIC34). The output I have obtained follows the 256 bit clock mode, but I have made some tests and DOUT pins doesn't seem like high impedance when unused, so I am afraid to damage the component linking together DOUT_A and DOUT_B. I have also read the registers and register 8 is properly written. Furthermore I don't understand why the DOUT pins during the resting periods sometimes have a low level and other times a high level. Is it possible that I have already damaged the DOUT pins in some tests before (where I didn't use ADCs) during which I had DOUT_A and DOUT_B shortcircuited, and high impedance is not working anymore?

    Thanks

    Best regards

  • Hello Ivan,

    TDM is possible with the two blocks but it is not possible to achieve on the EVM unless you have some external processor. Might you have an Audio Precision?

    Regards,
    Aaron

  • Hi Aaron,

    unfortunately I don't have an external processor right now, but I need to test the possibility to connect the two blocks to the same interface. I remind you that I don't need a completely working communication on the audio serial data, but only need to see the DOUT pins of the codec.

    I have followed the instructions on the application note "Using TDM Function to Interface Four TLV320AIC33 Codecs With a Single Host Processor" (SLAA301) which states:

    'On the AIC33EVM-PDK system, the AIC33 audio data is streamed, between the system and a PC,
    through the onboard TAS1020B processor on the USB-MODEVM board. The firmware on the TAS1020B
    processor cannot work in TDM mode. Thus, an external host processor is needed to interface with these
    AIC33 devices as the audio data bus master; or one of the AIC33 should be configured as the audio data
    bus master.'

    I have configured block A as audio data bus master (BCLK and WCLK as outputs) and block B as a slave, 256 clock transfer mode, DSP mode and DOUT in high impedance when valid data is not being sent. But it seems to be not in high impedance, I have connected high value pull-up resistors to DOUT pins, but even with these the outputs sometimes are low (when data are not sent). Do you know what can be the problem?

    Why do you say that TDM is not achievable on EVM? On the application note it is shown as possible.

    Below my code, copied and modified from the AN 301.

    #############################################################
    # setup for 4 AIC33 EVM boards Stocked on a USB-MODEVM
    #
    # uses I2C interface and TDS audio data Interface
    #
    # Wendy Fang, 2006.3.29
    ##############################################################
    #
    # -- Digital Interfaces
    # The first EVM board (A1A0=00) is the TDM master to generate BCLK and WCLK
    #
    # -- Audio Inputs
    # For all 4 Boards, the audio input path are the same and:
    # MIC3 -> ADC PGA ----------------> ADC -> DOUT
    # But ONLY one EVM ADCs is powered up and ONLY one MICBIAS should be enabled.
    #
    # -- Audio Outputs
    # Only one EVM outputs will be setup and enabled at a time and it is:
    # DIN --> Digital Volume Control -> DAC -> DAC_R1 -> Analog Volume Control -> HPOUT
    #
    #############################################################
    # -- input from MIC3
    # -- add power up MICBIAS to 2.5V
    #
    # -- Output with pop reduction
    # -- Output at Capless mode from HPOUT
    #############################################################
    ##############
    # Interfaces
    ##############
    # Since Fsref=44.1K (For: MCLK=11.2896MHz), we do not use PLL and FS=Fsref
    #
    i i2cfast
    w 30 00 00
    w 32 00 00
    w 30 01 80
    w 32 01 80
    # reg 07 - codec datapath
    # L-DAC plays DIN left data and R-DAC plays right one
    w 30 07 8A
    w 32 07 8A
    # reg 08/09/10 - Audio Interface
    # The first codec is the master (-256s) and the rest are slaves;
    # DOUT all at tri-state when valid data is bit being sent
    # DSP/16-bit mode with slot (n*2*16 bits, n=0, 1, 2, 3) delay
    w 30 08 E0
    w 32 08 20
    w 30 09 48
    w 32 09 48
    w 30 0A 00
    w 32 0A 80
    ##############
    # Input Path
    ##############
    # reg 17/18 - MIC3L for Left ADC and MIC3R for right ADC
    w 30 11 0F F0
    # regs 25 - Power up MICBIAS to 2.5V for only one of EVMs
    w 30 19 00
    w 32 19 80
    # reg 19/22 - power up ADC
    w 30 13 7C
    w 32 13 7C
    w 30 16 7C
    w 32 16 7C
    # regs 15/16 - unmute ADC PGA and set to 0dB
    w 30 0F 00 00
    w 32 0F 00 00
    ##############
    # Output Path
    ##############
    # reg 14 - if at AC-Cap mode
    #w 32 0E 80
    # reg 42 - driver power ON Pop Control
    w 30 2A 6C
    w 32 2A 6C
    ######
    # reg 37 DAC POWER CONTROL/ reg 38 HPCOM CONFIG
    # Power up L and R DACs
    # HPCOML/R as Headphone COM for Cap-Less mode
    w 32 25 D0 08
    # regs 43/44 - Unmute DAC L/R and set the Digital Volumes to 0dB
    w 32 2B 00 00
    ######
    # reg 47 - HPLOUT from Left DAC routed to HPLOUT @ 0dB
    w 32 2F 80
    # reg 51 - HPLOUT Level = 0dB, not muted, and powered up
    w 30 33 04
    w 32 33 0D
    # reg 58 - HPLCOM Level, set HPLCOM at tri-state with PD
    w 30 3A 04
    w 32 3A 04
    # reg 64 - HPROUT from Right DAC routed to HPROUT @ 0dB
    # reg 65 - HPROUT Level = 0dB, not muted, and powered up
    w 30 40 80 04
    w 32 40 80 0D
    # reg 72 - HPRCOM Level, set HPRCOM at tri-state with PD
    w 30 48 04
    w 32 48 04

  • Hello Ivan,

    My apologies, I was previously mistaken about not achieving TDM on the EVM. I took the code you provided above, slightly modified it, and ran it. The only change I made was to route MIC3L and R  on the B block so I can see the two sets of data.  I was able to achieve TDM with no issues. I have attached the code I used in a .txt file. 

    There are a couple of things that I want to note/comment on:

    1. Make sure the EVM and USB-MODEVM are set up correctly. The USB-MODEVM should have SW-2.4 and 2.8 switched to the right. Everything else to the left. This will disable BCLK and WCLK from being generated by the USB-MODEVM.

    2. Make sure MCLK_A, BCLK_A, WCLK_A, and DOUT_A are tied to their B block counterpart. This is done on header J17. 

    3. Tristate will not pull the output high... it will make it high-Z. Dout will hold the value of the last bit transmitted. This is why you may see it toggle from Low to High or vice versa. 

    Find the attached config here:  

    AIC34_TDM_MIC3L.txt
    w 30 00 00
    w 32 00 00
    w 30 01 80
    w 32 01 80
    # reg 07 - codec datapath
    # L-DAC plays DIN left data and R-DAC plays right one
    w 30 07 8A
    w 32 07 8A
    # reg 08/09/10 - Audio Interface
    # The first codec is the master (-256s) and the rest are slaves;
    # DOUT all at tri-state when valid data is bit being sent
    # DSP/16-bit mode with slot (n*2*16 bits, n=0, 1, 2, 3) delay
    w 30 08 E0
    w 32 08 20
    w 30 09 48
    w 32 09 48
    w 30 0A 00
    w 32 0A 80
    ##############
    # Input Path
    ##############
    # reg 17/18 - MIC3L for Left ADC and MIC3R for right ADC
    w 30 11 0F F0
    w 32 11 0F F0
    # regs 25 - Power up MICBIAS to 2.5V for only one of EVMs
    w 30 19 00
    w 32 19 80
    # reg 19/22 - power up ADC
    w 30 13 7C
    w 32 13 7C
    w 30 16 7C
    w 32 16 7C
    # regs 15/16 - unmute ADC PGA and set to 0dB
    w 30 0F 00 00
    w 32 0F 00 00
    ##############
    # Output Path
    ##############
    # reg 14 - if at AC-Cap mode
    #w 32 0E 80
    # reg 42 - driver power ON Pop Control
    w 30 2A 6C
    w 32 2A 6C
    ######
    # reg 37 DAC POWER CONTROL/ reg 38 HPCOM CONFIG
    # Power up L and R DACs
    # HPCOML/R as Headphone COM for Cap-Less mode
    w 32 25 D0 08
    # regs 43/44 - Unmute DAC L/R and set the Digital Volumes to 0dB
    w 32 2B 00 00
    ######
    # reg 47 - HPLOUT from Left DAC routed to HPLOUT @ 0dB
    w 32 2F 80
    # reg 51 - HPLOUT Level = 0dB, not muted, and powered up
    w 30 33 04
    w 32 33 0D
    # reg 58 - HPLCOM Level, set HPLCOM at tri-state with PD
    w 30 3A 04
    w 32 3A 04
    # reg 64 - HPROUT from Right DAC routed to HPROUT @ 0dB
    # reg 65 - HPROUT Level = 0dB, not muted, and powered up
    w 30 40 80 04
    w 32 40 80 0D
    # reg 72 - HPRCOM Level, set HPRCOM at tri-state with PD
    w 30 48 04
    w 32 48 04
    
    *** DOUT_A should be tied to DOUT_B
    *** Connect input to MIC3L_B on J13
    *** Make sure MCLK, BCLK and WCLK are tied to both blocks
    

    Please let me know if you have any more questions or trouble. If you would like, please send me how your EVM is set up and I can take a look. It would also be nice if you can share scope captures of what you are seeing. It would be great if you can send over BCLK, WCLK, and DOUT. 

    Regards,

    Aaron