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TLV320ADC3100: BCLK settings

Part Number: TLV320ADC3100

Hi team,

I'm trying to understand how to set BCLK of TLV320ADC3100, my understanding is that in slave mode the host should supply BCLK which should be  2*sample frequency* word length (how many bits) to the ADC.

When the I2S word length is 16 bits and sample frequency is 44.1kHz, the BCLK should be 1.4112MHz, while in the example on the datasheet the BCLK is 2.8224MHz at 16 bits word length, how to understand this?



  • George, 

    On the EVM, the ADC3100 device runs in slave mode, and the TAS1020B USB audio processor sets the BCLK frequency.  the BCLK frequency is hard set to 2.8224MHz on this processor for Fs = 44.1kHz.  This is to accommodate up to 32 bit data word length from the slave device.  So when the ADC3100 is configured for 16-bit data,  it will transmit 16bits, and there will be 16 bits of padding. 

    Does this make sense?

    -Steve wilson

  • Hi Steve,

    Thanks for the reply, so you mean the BCLK frequency could be set higher than 2*sample frequency* word length and for the redundant bits we just neglect them?

    Also, can you help to have a look at below configuration of the ADC clock, can it work? What happens if the clock wasn't configured correctly? 



  • George, 

    Yes, the BCLK frequency doesn't have to be exactly FS*2*data word length.  BCLK must be at least that frequency, but there can be pad bits.  

    In the case of the EVM,  the device supports data word lengths of 16-32 bits. We wanted to ensure that users could use the 32bit word length without requiring that the USBMODEVM motherboard firmware be rewritten.  

    your settings seem fine to me assuming you are not using the PLL and the device is a ASI Slave.

    If your clock settings were wrong,  you could get bad data in a number of forms,  anything from incorrect data rate, to skipped/repeated samples or just incoherent noise.

    Best regards,

    -Steve Wilson