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DIX4192: DIX4192 - I2S data

Vojtech Kana
Prodigy 190 points
Part Number: DIX4192
Other Parts Discussed in Thread: TAS5634

Hi,

I tried run I2S data via DIX4192. Scheme attached below.

Audio signal input RX1+ and RX1-. I2S data from PORT B (SDOUTB) didnt appear as well as clock from RXCKO. LRCKB and BCKB signals are correct (PWM is generated).

I communicate via I2C: 

Address Register                             value

0x01                                                     0x3A

0x03                                                      0x01

0x05                                                      0x29

0x06                                                      0x01

0x07                                                      0x10

What else registers has to been set?

Thank you very much.

Regards 

Vojtech Kana

  • 0
    TI__Mastermind 23050 points

    Hi Vojtech,

    First if you are operating in master mode with clocks derived from the DIR, then you should set the Port B master clock to RXCKO in register 0x06 instead of the MCLK input. Also by default the receiver reference clock is set to RXCKI, but you do not have a clock at this pin so you should set this to MCLK by writing 0x08 to register 0x0D.

    Best,

    Zak

  • 0 in reply to Zak Kaye
    Prodigy 190 points

    Hi Zak,

    I have done what you recommended, but now do not appear PWM on the rest of I2S (PORT B) data as well as RXCKO.

    Registers now: 

    0x01                     0x3A

    0x03                      0x01

    0x05                      0x29

    0x06                      0x09

    0x07                      0x10

    0x0D                     0x08

    Could you verified it on TAS5634 EVM, if you can?

    Regards,

    Vojtech 

  • 0 in reply to Vojtech Kana
    TI__Mastermind 23050 points

    Hi Vojtech,

    What is your input source? If you do not see a signal on the RXCKO you may first need to enable the clock output on this pin by setting RXCKOE bit high in register 0x0E. By default this is disabled. If you still do not see a clock on RXCKO after this then that means that the DIR was not able to lock on to the input signal and recover a clock. To verify this, you can check the receiver status registers, register 13 and 14. This will tell you what your maximum allowed sample rate is (so you can verify if you are attempting to set the dividers to an unsupported rate) and also what the lock status of the DIR and PLL2 are.