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LM49450: LM49450 phase delay issue

Feng bin Su
Expert 8120 points
Part Number: LM49450

Hi team,

My customer is using our LM49450 for their headphone design and they have face the phase delay issue which is very similar with a post on e2e.

https://e2e.ti.com/support/audio/f/6/t/819388?tisearch=e2e-sitesearch&keymatch=lm49450

 

In this thread, you have suggested to set register 0x00 from 21 to 61 corrected the phase delay.

And we also have customer to modify the register 0x00 from 61 to 21. Their phase delay have improved from 5X  degree to 28 degree but their THD+n has violate the spec of theirs (>-60db).

So, may I have your help to know how to fix the phase delay issue and also don't influence the THD+n performance? Their fMCLK= 3.079MHz and their register setting is as below. Thank for your kindly help.

Register Addr 0x0 = 0x61

Register Addr 0x1 = 0x0

Register Addr 0x2 = 0x26

Register Addr 0x3 = 0x0

Register Addr 0x4 = 0x0

Register Addr 0x5 = 0x0

Register Addr 0x6 = 0x0

Register Addr 0x7 = 0xb

Register Addr 0x8 = 0xb

Register Addr 0x9 = 0x0

Register Addr 0xa = 0x0

Register Addr 0xb = 0x0

Register Addr 0xc = 0x0

Register Addr 0xd = 0x0

Register Addr 0xe = 0x0

 

Register 0X00=21H   00100001

 

  Register 0X00=61H    01100001

 

 

  • 0
    TI__Guru* 84915 points

    Hi, Feng,

    This problem seems to be associated to the sampling rate. Could you provide a capture of the I2S clock lines that the customer is using, please? This would be helpful to have a better approach to this issue.

    Does the customer have different results if he uses values like 0x01, 0x41, 0x09 or 0x49?

    Any other information you could provide will be appreciated.

    Best regards,
    Luis Fernando Rodríguez S.

  • 0 in reply to Luis Fernando Rodriguez S.
    TI__Guru* 84915 points

    Hi, Feng,

    I'm closing this e2e thread due to the inactivity. However, feel free to post any additional information or feedback that you have about this issue. We will be glad to provide support.

    Best regards,
    Luis Fernando Rodríguez S.

  • 0 in reply to Luis Fernando Rodriguez S.
    TI__Expert 8120 points

    Hi Luis,

    Thank for your help. We spend some time to do the test. We also think that it is related with clock structure. Please refer the clock waveform as below.

     fMCLK (R18)= 12.288MHz

    fI2C_clk (R19)=3.053MHz

    fI2C_ws (R21)=48KHz

    #2 register setting difference 

    Register Addr 0x0 = 0x61

    Register Addr 0x1 = 0x3

    phase delay fail:-58 degree

    #3 register setting difference 

    Register Addr 0x0 = 0x61

    Register Addr 0x1 = 0x0

    Register Addr 0x2 = 0x49

    Register Addr 0x7 = 0x14

    phase delay pass:17.96 degree

    THD+N Fail : -29.68( Spec>=60dB)

    May I know whether there is a setting can pass phase delay and THD+n at same time? Please let me know your recommendation setting and debug flow.

    We would like to make the debug flow more efficiency. Thanks.