Hello,
Our customer plans to stuff 6pcs of PCM1791A at TDMCA mode.
In that case BCK become 256fs, can they use 128fs SCK input?
It looks like very tough situation that DAC System clock is slower than inputted TDM BCK cycle.
On the datasheet there is no limitation of lowest SCK cycle at TDMCA mode.
Regards,
Mochizuki