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TLV320ADC3100: TDM slots clarification

M.A.M
Expert 8455 points
Part Number: TLV320ADC3100
Other Parts Discussed in Thread: TLV320ADC3140

Hi,

1) Can you confirm that this device is limited to max TDM8 (8 slots for 24bit data), and not TDM16?

2) What other affordable ADC supports TDM16 or more?

Thanks.

B.r M.A.M

  • 0
    TI__Expert 8455 points

    Hi,

    Adding to question #1:

    - Would the device work with TDM16 if its data packets stays in the first half of the frame? Keeping DOUT tri-stated until next frame?

    I am thinking of using

    Fs = 48000
    WL = 24 bits
    Mclk=Bclk = 24.576MHz
    AOSR = 128
    MADC = 2
    NADC = 2  => ADC_IN clk = 24,576MHz
    PLL => Disabled
    Filter = PRB_R1

    It is just that the Master's Word Clock "WCK" restarts after 16x32bit clock periods (512bits), and I hope that ADC3100 can adapt (using tri-state when data is not being sent) to that operation with above register settings, provided that the ADC3100 channel offsets place its sent data in the first half of the TDM frame?

    The datasheet does not explain well how WCK and ADC start-of-conversion relates.

    B.r M.A.M

  • 0 in reply to M.A.M
    TI__Mastermind 30030 points

    M.A.M,

    The real limitation for the ADC3101 is going to be the Audio bus timing constraints.  the BCLK high/low time in slave mode has a minimum of 35nsec each for a period of 70nSec. so a BCLK of 24.576Mhz would exceed the timing requirements.  

    The TLV320ADC3140 is a 4 channel device that can do higher BCLKs and has a very flexible ASI bus with the ability to assign up to 64 slots.  of course at 48khz 64 slots is not possible  due to timing requirements, but for 16khz or 8khz it would be possible. 

    best regards,

    -Steve wilson

  • 0 in reply to Steve-Wilson
    TI__Expert 8455 points

    Hi again,

    Would halving the BCK to 12MHz somehing  help, and use the PLL instead? Please elaborate. The ADC must be low cost... ADC3100 is preferred.

    It is for my customer.

    B.r M.A.M

  • 0 in reply to M.A.M
    TI__Mastermind 30030 points

    M.A.M. 

    A BCLK under 14MHz is no problem.  The PLL will help to generate the internal system clock,   but it sounded like you wanted 16 32 bit channels right? 

    ADC3100 can tristate the DOUT no problem,  the Data channel location will depend on which Data format is chosen,  but for example in DSP mode,  a zero offset will place the data in the first two slots,  the data offset can be up to 256 bits. 

    best regards,

    -Steve Wilson