I'm working on a design which might use the SRC4392 as SPDIF receiver to SRC to I2S slave.
What I need is totally automatic SPDIF receiving and sample rate converting independent of SPDIF sampling rate.
Right now we use the CS8422, but I'd prefer to use the SRC4392 for other reasons (CDAT and UDAT buffers).
The Receiver PLL1 Configuration Registers make me think that this is not possible, because the PLL1 settings
need to be adjusted when SPDIF input sample rate changes.
Real life application would be:
SPDIF input: any sample rate between 44.1kHz and 192kHz
I2S output: 100kHz sample rate, with an MCLK of 25.6MHz
Is that possible with fixed PLL1 settings?