Other Parts Discussed in Thread: SRC4392, DIX9211, PLL1707
We are using DIX4192 in an application wherein we want the DIX4192 to accept a substantially jittered AES3 signal, and to remove the jitter from that signal and re-transmit the non-jittered result from the DIX4192's DIT.
Injecting a low-jittered AES signal into AES3 INPUT XLR, the same low jitter appears as the result at AES3 OUTPUT XLR. So it seems the intrinsic jitter introduced by our design and by DIX4192 is acceptably low.
But when injecting a highly-jittered signal into AES3 INPUT XLR, I am seeing no reduction of that jitter at AES3 OUTPUT XLR.
What is the best way to configure the DIX4192 so as to achieve optimal jitter reduction?
Currently, this is how we are using DIX4192, per the register settings shown. We could change these settings, if a different configuration will produce good jitter reduction.
AES3 INPUT XLR -> DIR of DIX4192 -> PortA of DIX4192 -> PortB of DIX4192 -> DIT of DIX4192 -> AES3 OUTPUT XLR
reg# value
0x01, 0x00); // Inititally keep all function blocks in Power-Down Mode.
0x03, 0x28); // Configure Port A Cntrl Rgstr 1 (unmute; use DIR as data source; Master mode).
0x04, 0x08); // Configure Port A Cntrl Rgstr 2 (RXCKO = master clock source; Divide by 128).
0x05, 0x00); // Configure Port B Cntrl Rgstr 1 (all settings = Default).
0x06, 0x00); // Configure Port B Cntrl Rgstr 2 (MCLK = master clock source; Divide by 128).
0x07, 0x0c); // Configure Port B to be the DIT data source; BLS pin to be an Output.
0x08, 0x03); // Configure Transmitter Cntrl Rgstr 2 such that the AES3 transmitter line driver outputs are initially forced low and muted.
0x09, 0x01); // Configure Transmitter Cntrl Rgstr 3 such that initially, the DIT UA buffers are updated via the SPI host interface.
0x0d, 0x00); // Configure Receiver Cntrl Rgstr 1 (all settings = Default).
0x0e, 0x0d); // Enable RXCKO; Auto-Mute DIR data when a loss of lock is indicated.
0x0f, 0x44); // PLL1 Configuration Rgstr 1 -> set P=4, J=16, D=0, since REF_MCLK = 24.576MHz.
0x10, 0x00); // PLL1 Configuration Rgstr 2 -> set P=4, J=16, D=0, since REF_MCLK = 24.576MHz.
0x11, 0x00); // PLL1 Configuration Rgstr 3 -> set P=4, J=16, D=0, since REF_MCLK = 24.576MHz.
// Configure all used function blocks to operate normally (i.e. not Power-Down Mode), but keep transmitters muted.
0x01, 0x3e);
// Ensure all chips' offset calibration cycles finish.
delay_ms(500);
0x08, 0x00); // (Unmute and enable the AES3 transmitter line driver outputs)