Sorry. Re-posting from another thread. Does anyone from TI monitor this forum?
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Vikas,
I am having the same problem with my AIC3204. The basic functionality works fine, but I can't seem to get the beep generator working. I've notice several postings of questions/problems, but no one has come back saying they got it working. Is there some power block that needs to be enabled?
I have followed the slaa446 document, but no beep. Here's my settings:
void aic3204_beep()
{
AIC3204_rset( 0, 0 );
AIC3204_rset( 74, 0x5d ); //1.2 seconds @ 48000 sps
AIC3204_rset( 75, 0xc0 );
AIC3204_rset( 76, 0x23 );
AIC3204_rset( 77, 0xFB );
AIC3204_rset( 78, 0x7A );
AIC3204_rset( 79, 0xD7 );
AIC3204_rset( 71, 0x80 ); //turn on beep
}
And here's the initialization, which works fine for audio.
/* ------------------------------------------------------------------------ *
* *
* aic3204_init( ) *
* *
* ------------------------------------------------------------------------ */
void aic3204_init(void)
{
/* Configure AIC3204 */AIC3204_rset( 0, 0 ); // Select page 0
AIC3204_rset( 1, 1 ); // Reset codecUSTIMER_delay(1000);
AIC3204_rset( 0, 1 ); // Point to page 1
AIC3204_rset( 1, 8 ); // Disable crude AVDD generation from DVDD
AIC3204_rset( 2, 1 ); // Enable Analog Blocks, use LDO power
/* PLL and Clocks config and Power Up */
AIC3204_rset( 0, 0 ); // Select page 0
AIC3204_rset( 27, 0x0d ); // BCLK and WCLK is set as output from AIC3204(Master)
AIC3204_rset( 28, 0x00 ); // Data ofset = 0
AIC3204_rset( 4, 3 ); // PLL setting: PLLCLK <- MCLK, CODEC_CLKIN <-PLL CLK
AIC3204_rset( 6, 8 ); // PLL setting: J=8
AIC3204_rset( 7, 15 ); // PLL setting: HI_BYTE(D)
AIC3204_rset( 8, 0xdc ); // PLL setting: LO_BYTE(D)
AIC3204_rset( 30, 0x88 ); // For 32 bit clocks per frame in Master mode ONLY
// BCLK=DAC_CLK/N =(12288000/8) = 1.536MHz = 32*fs
// For 48 KHz sampling
AIC3204_rset( 5, 0x91 ); // PLL setting: Power up PLL, P=1 and R=1
AIC3204_rset( 13, 0x00 ); // Hi_Byte(DOSR) for DOSR = 128 decimal or 0x0080 DAC oversamppling
AIC3204_rset( 14, 0x80 ); // Lo_Byte(DOSR) for DOSR = 128 decimal or 0x0080
AIC3204_rset( 20, 0x80 ); // AOSR for AOSR = 128 decimal or 0x0080 for decimation filters 1 to 6
AIC3204_rset( 11, 0x88 ); // Power up NDAC and set NDAC value to 8
AIC3204_rset( 12, 0x82 ); // Power up MDAC and set MDAC value to 2
AIC3204_rset( 18, 0x88 ); // Power up NADC and set NADC value to 8
AIC3204_rset( 19, 0x82 ); // Power up MADC and set MADC value to 2
/* DAC ROUTING and Power Up */
AIC3204_rset( 0, 0x01 ); // Select page 1
AIC3204_rset( 12, 0x08 ); // LDAC AFIR routed to HPL
AIC3204_rset( 13, 0x08 ); // RDAC AFIR routed to HPR
AIC3204_rset( 0, 0x00 ); // Select page 0
AIC3204_rset( 64, 0x02 ); // Left vol=right vol
AIC3204_rset( 65, 0x00 ); // Left DAC gain to 0dB VOL; Right tracks Left
AIC3204_rset( 63, 0xd4 ); // Power up left,right data paths and set channel
AIC3204_rset( 0, 0x01 ); // Select page 1
AIC3204_rset( 16, 15 ); // Unmute HPL set gain
AIC3204_rset( 17, 15 ); // Unmute HPR set gain
AIC3204_rset( 10, 0x33 ); // HP powered from LDOIN, CM voltage = 1.65V
AIC3204_rset( 20, 0x25 ); //De-pop
AIC3204_rset( 9, 0x30 ); // Power up HPL,HPR
AIC3204_rset( 0, 0x00 ); // Select page 0
USTIMER_delay(3000);
/* ADC ROUTING and Power Up */
AIC3204_rset( 0, 1 ); // Select page 1
AIC3204_rset( 52, 0x30 ); // Line Input Jack (IN2)
// IN2_L to LADC_P through 40 kohm
AIC3204_rset( 55, 0x30 ); // IN2_R to RADC_P through 40 kohmm
AIC3204_rset( 54, 0xc0 ); // CM_1 (common mode) to LADC_M through 40 kohm
AIC3204_rset( 57, 0xc0 ); // CM_1 (common mode) to RADC_M through 40 kohm
AIC3204_rset( 59, 20 ); // MIC_PGA_L gain in db
AIC3204_rset( 60, 20 ); // MIC_PGA_R gain in db
AIC3204_rset( 0, 0 );
AIC3204_rset( 81, 0xc0 ); // Powerup Left and Right ADC
AIC3204_rset( 82, 0x00 ); // Unmute Left and Right ADC
USTIMER_delay(5000);}
Thx,
MikeH
